公开(公告)号：US20160364899A1

公开(公告)日：2016-12-15

申请号：US14735707

申请日：2015-06-10

Applicant: Apple Inc.

Inventor： Abdulkadir U. Diril ,  Adam T. Moerschell ,  Anthony P. DeLaurier

IPC: G06T15/04 ,  G06T1/20

CPC classification number: G06T15/04 ,  G06F3/14 ,  G06T1/20 ,  G06T2200/28 ,  G06T2210/36 ,  G09G5/14 ,  G09G5/363 ,  G09G5/39 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/021 ,  G09G2340/04

Abstract: Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.

Abstract translation: 公开了关于确定图形纹理的指定级别的细节的位置的技术。 在一些实施例中，设备包括纹理处理电路，其被配置为接收指定用于图形纹理的存储mipmap的链中的特定mipmap的信息，并确定特定mipmap的偏移地址。 在这些实施例中，纹理处理电路被配置为通过对指示图形处理元件中的mipmap的链的最大潜在链大小的值进行操作来确定偏移地址。 在这些实施例中，操作包括基于纹理的大小掩蔽该值的高位，并且基于所存储的mipmap中的指定的mipmap的位置来屏蔽该值的较低位。 公开的技术可以减少配置成确定偏移的电路的功率消耗和/或电路的面积。

公开(公告)号：US10354431B2

公开(公告)日：2019-07-16

申请号：US14735707

申请日：2015-06-10

Applicant: Apple Inc.

Inventor： Abdulkadir U. Diril ,  Adam T. Moerschell ,  Anthony P. DeLaurier

IPC: G06T15/04 ,  G06T1/20 ,  G09G5/39

Abstract: Techniques are disclosed relating to determining the location of a specified level of detail for a graphics texture. In some embodiments, an apparatus includes texture processing circuitry configured to receive information specifying a particular mipmap in a chain of stored mipmaps for a graphics texture and determine an offset address for the particular mipmap. In these embodiments, the texture processing circuitry is configured to determine the offset address by operating on a value that indicates a greatest potential chain size for chains of mipmaps in a graphics processing element. In these embodiments, the operating includes masking upper bits of the value based on a size of the texture and masking lower bits of the value based on a position of the specified mipmap in the chain of stored mipmaps. Disclosed techniques may reduce power consumption and/or area of circuitry configured to determine the offset.

公开(公告)号：US20170221550A1

公开(公告)日：2017-08-03

申请号：US15009200

申请日：2016-01-28

Applicant: Apple Inc.

Inventor： Abdulkadir U. Diril ,  Adam T. Moerschell ,  Anthony P. DeLaurier

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C19/00

Abstract: Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.

公开(公告)号：US09811875B2

公开(公告)日：2017-11-07

申请号：US14482828

申请日：2014-09-10

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Adam T. Moerschell ,  James S. Blomgren

IPC: G09G5/00 ,  G06T1/60 ,  G06T15/04

CPC classification number: G06T1/60 ,  G06T15/04

Abstract: Techniques are disclosed relating to a cache configured to store state information for texture mapping. In one embodiment, a texture state cache includes a plurality of entries configured to store state information relating to one or more stored textures. In this embodiment, the texture state cache also includes texture processing circuitry configured to retrieve state information for one of the stored textures from one of the entries in the texture state cache and determine pixel attributes based on the texture and the retrieved state information. The state information may include texture state information and sampler state information, in some embodiments. The texture state cache may allow for reduced rending times and power consumption, in some embodiments.

公开(公告)号：US09761303B2

公开(公告)日：2017-09-12

申请号：US15009200

申请日：2016-01-28

Applicant: Apple Inc.

Inventor： Abdulkadir U. Diril ,  Adam T. Moerschell ,  Anthony P. DeLaurier

IPC: G11C11/00 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C7/22 ,  G11C19/00

Abstract: Techniques relating to providing clock signals to a storage element. Generally, different portions of a given storage element may be clocked according to different schemes. This technique may be pertinent to a storage element that has a portion for which the associated bit values do not change frequently relative to another portion of the storage element. For such a storage element, a high-frequency portion may be clocked upon an access to the storage element, while a low-frequency portion may be clocked only if there is a change in the associated bit values. This technique can be applied to various storage elements, including registers and FIFO buffer entries. An apparatus may be designed such that the low-frequency and high-frequency portions of a storage element do not change during operation. Alternatively, the low-frequency and high-frequency portions of the storage element may be changeable based on a current operating mode of the apparatus.

公开(公告)号：US20160071232A1

公开(公告)日：2016-03-10

申请号：US14482828

申请日：2014-09-10

Applicant: Apple Inc.

Inventor： Benjiman L. Goodman ,  Adam T. Moerschell ,  James S. Blomgren

IPC: G06T1/60 ,  G06T1/20 ,  G06T7/00 ,  G06T7/40 ,  G06T11/00

CPC classification number: G06T1/60 ,  G06T15/04

Abstract: Techniques are disclosed relating to a cache configured to store state information for texture mapping. In one embodiment, a texture state cache includes a plurality of entries configured to store state information relating to one or more stored textures. In this embodiment, the texture state cache also includes texture processing circuitry configured to retrieve state information for one of the stored textures from one of the entries in the texture state cache and determine pixel attributes based on the texture and the retrieved state information. The state information may include texture state information and sampler state information, in some embodiments. The texture state cache may allow for reduced rending times and power consumption, in some embodiments.

Abstract translation: 公开了与被配置为存储用于纹理映射的状态信息的高速缓存相关的技术。 在一个实施例中，纹理状态高速缓存包括被配置为存储与一个或多个存储纹理相关的状态信息的多个条目。 在该实施例中，纹理状态高速缓存还包括纹理处理电路，其被配置为从纹理状态高速缓存中的一个条目中检索存储的纹理之一的状态信息，并且基于纹理和检索到的状态信息来确定像素属性。 在一些实施例中，状态信息可以包括纹理状态信息和采样器状态信息。 在一些实施例中，纹理状态高速缓存可以允许减少渲染时间和功耗。