公开(公告)号：US09529718B2

公开(公告)日：2016-12-27

申请号：US14569175

申请日：2014-12-12

Applicant: Advanced Micro Devices, Inc.

Inventor： Syed Ali R. Jafri ,  Yasuko Eckert ,  Srilatha Manne ,  Mithuna S. Thottethodi ,  Gabriel H. Loh

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0833 ,  G06F12/0868 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/121 ,  G06F12/126 ,  G06F12/128 ,  G06F2212/62 ,  Y02D10/13

Abstract: To efficiently transfer of data from a cache to a memory, it is desirable that more data corresponding to the same page in the memory be loaded in a line buffer. Writing data to a memory page that is not currently loaded in a row buffer requires closing an old page and opening a new page. Both operations consume energy and clock cycles and potentially delay more critical memory read requests. Hence it is desirable to have more than one write going to the same DRAM page to amortize the cost of opening and closing DRAM pages. A desirable approach is batch write backs to the same DRAM page by retaining modified blocks in the cache until a sufficient number of modified blocks belonging to the same memory page are ready for write backs.

Abstract translation: 为了有效地将数据从高速缓存传输到存储器，期望将与存储器中的相同页面相对应的更多数据加载到行缓冲器中。 将数据写入当前未加载到行缓冲区的内存页面时，需要关闭旧页面并打开新页面。 两种操作都消耗能量和时钟周期，并可能延迟更多关键的存储器读取请求。 因此，期望具有多于一个写入同一DRAM页面的写入以分摊打开和关闭DRAM页面的成本。 期望的方法是通过将修改的块保留在高速缓存中来批量回写到相同的DRAM页面，直到属于同一存储器页面的足够数量的修改的块准备好回写。

公开(公告)号：US20160224397A1

公开(公告)日：2016-08-04

申请号：US14610662

申请日：2015-01-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Manish Arora ,  Can Hankendi ,  Syed Ali R. Jafri ,  Andrew G. Kegel

IPC: G06F9/52 ,  G11C7/10 ,  G06F12/02 ,  G06F9/50 ,  G06F9/46

CPC classification number: G06F9/485 ,  G06F12/0246 ,  G06F2212/7201 ,  H04W4/02 ,  H04W4/029 ,  H04W4/50

Abstract: In one form, a data processing system includes volatile and non-volatile memory, a central processing unit, and at least one peripheral device. The central processing unit executes a selected one of a plurality of software applications as directed by an operating system by transferring the selected software application from the non-volatile memory to the volatile memory and executing instructions associated with the selected software application from the volatile memory. The at least one peripheral device includes a real-time clock for defining execution contexts for the plurality of software applications. The data processing system further includes a usage pattern analyzer adapted to store history information associated with an execution context for each of the plurality of software applications, and to use the history information to direct the operating system to take at least one action based on the history information.

Abstract translation: 在一种形式中，数据处理系统包括易失性和非易失性存储器，中央处理单元和至少一个外围设备。 中央处理单元通过将所选择的软件应用程序从非易失性存储器传送到易失性存储器并且从易失性存储器执行与所选择的软件应用程序相关联的指令，由操作系统指导执行多个软件应用程序中的选定的一个。 所述至少一个外围设备包括用于定义多个软件应用的执行上下文的实时时钟。 所述数据处理系统还包括使用模式分析器，其适于存储与所述多个软件应用中的每一个的执行上下文相关联的历史信息，并且使用所述历史信息来指示所述操作系统基于所述历史记录采取至少一个动作 信息。