公开(公告)号：US20150293854A1

公开(公告)日：2015-10-15

申请号：US14253785

申请日：2014-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Johnsy Kanjirapallil John ,  Phillip E. Nevius ,  Robert G. Gelinas

IPC: G06F12/08 ,  G11C29/44

CPC classification number: G06F12/0864 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0873 ,  G06F12/0888 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/28 ,  G06F2212/283 ,  G06F2212/284 ,  G06F2212/403 ,  G11C15/00 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/0409

Abstract: A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.

Abstract translation: 一种管理高速缓存存储器的方法包括以对应于在访问请求中指定的地址的主要索引访问高速缓冲存储器。 确定在主索引处访问高速缓冲存储器不会导致在具有无错状态的高速缓存行上的高速缓存命中。 响应于该确定，主索引被映射到次索引，并且该地址的数据被写入到次级索引处的高速缓存行。

公开(公告)号：US09424195B2

公开(公告)日：2016-08-23

申请号：US14253785

申请日：2014-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Johnsy Kanjirapallil John ,  Phillip E. Nevius ,  Robert G. Gelinas

IPC: G11C29/44 ,  G06F12/08 ,  G06F12/12 ,  G06F11/10 ,  G11C15/00 ,  G11C29/04

CPC classification number: G06F12/0864 ,  G06F11/1064 ,  G06F12/0802 ,  G06F12/0811 ,  G06F12/0873 ,  G06F12/0888 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/28 ,  G06F2212/283 ,  G06F2212/284 ,  G06F2212/403 ,  G11C15/00 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/0409

Abstract: A method of managing cache memory includes accessing a cache memory at a primary index that corresponds to an address specified in an access request. A determination is made that accessing the cache memory at the primary index does not result in a cache hit on a cache line with an error-free status. In response to this determination, the primary index is mapped to a secondary index and data for the address is written to a cache line at the secondary index.

Abstract translation: 一种管理高速缓存存储器的方法包括以对应于在访问请求中指定的地址的主要索引访问高速缓冲存储器。 确定在主索引处访问高速缓冲存储器不会导致在具有无错状态的高速缓存行上的高速缓存命中。 响应于该确定，主索引被映射到次索引，并且该地址的数据被写入到次级索引处的高速缓存行。

公开(公告)号：US09189326B2

公开(公告)日：2015-11-17

申请号：US14048830

申请日：2013-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Johnsy Kanjirapallil John ,  Robert Gelinas ,  Vilas K. Sridharan ,  Phillip E. Nevius

IPC: G06F11/10 ,  G11C29/52 ,  G11C29/42 ,  G11C11/41 ,  G11C29/04

CPC classification number: G06F11/1008 ,  G11C11/41 ,  G11C29/42 ,  G11C29/52 ,  G11C29/78 ,  G11C2029/0409

Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.

Abstract translation: 可以使用错误状态缓冲区中的可重用条目实时检测和校正存储器阵列中的硬错误。 响应于从存储器阵列的部分读取的数据中的第一个错误，数据可以重写到存储器阵列和寄存器的一部分。 然后可以将重写的数据从寄存器写入错误状态缓冲器的条目，以响应于从寄存器读取的重写数据与从存储器阵列的部分读取的重写数据不同。

公开(公告)号：US20180052778A1

公开(公告)日：2018-02-22

申请号：US15243921

申请日：2016-08-22

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Adithya Yalavarti ,  Johnsy Kanjirapallil John

IPC: G06F12/12 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/0891

CPC classification number: G06F12/12 ,  G06F12/0811 ,  G06F12/0817 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/128 ,  G06F2212/1024

Abstract: A processing apparatus and a method of accessing data using cache hot set detection is provided that includes receiving a plurality of requests to access data in a cache. The cache includes a plurality of cache sets each including N number of cache lines. Each request includes an address. The apparatus and a method also includes storing, in a HSVC array, cache line victims of one or more of the plurality of cache sets determined to be hot sets. Each cache line victim includes a corresponding address that is determined, using a HSD array, to belong to the one or more determined cache hot sets based on a hot set frequency of a plurality of addresses mapped to the set in the cache.

公开(公告)号：US20150100848A1

公开(公告)日：2015-04-09

申请号：US14048830

申请日：2013-10-08

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Johnsy Kanjirapallil John ,  Robert Gelinas ,  Vilas K. Sridharan ,  Phillip E. Nevius

IPC: G06F11/10 ,  G11C29/52

CPC classification number: G06F11/1008 ,  G11C11/41 ,  G11C29/42 ,  G11C29/52 ,  G11C29/78 ,  G11C2029/0409

Abstract: Hard errors in the memory array can be detected and corrected in real-time using reusable entries in an error status buffer. Data may be rewritten to a portion of a memory array and a register in response to a first error in data read from the portion of the memory array. The rewritten data may then be written from the register to an entry of an error status buffer in response to the rewritten data read from the register differing from the rewritten data read from the portion of the memory array.

Abstract translation: 可以使用错误状态缓冲区中的可重用条目实时检测和校正存储器阵列中的硬错误。 响应于从存储器阵列的部分读取的数据中的第一个错误，数据可以重写到存储器阵列和寄存器的一部分。 然后可以将重写的数据从寄存器写入错误状态缓冲器的条目，以响应于从寄存器读取的重写数据与从存储器阵列的部分读取的重写数据不同。