公开(公告)号：US10054618B2

公开(公告)日：2018-08-21

申请号：US14829392

申请日：2015-08-18

Applicant: Apple Inc.

Inventor： Matthias Knoth ,  Conrad H. Ziesler ,  Toshinari Takayanagi

IPC: H01L29/10 ,  H01L21/66 ,  G01R19/25 ,  G01R19/00

CPC classification number: G01R19/2509 ,  G01R19/0084 ,  G06F1/30 ,  G06F11/00 ,  G06F11/3058

Abstract: In an embodiment, an integrated circuit includes a first circuit and a characterization circuit to capture a histogram of the supply voltage magnitude to the first circuit (or other characteristics of the first circuit). In various embodiments, the characterization circuit may: be located near the first circuit; include a sample/hold circuit that may sample the supply voltage in a short window of time and an ADC that is configured to converge to the sampled voltage over multiple orders of magnitude longer than the short window; be relatively small and low power; capture multiple histograms, e.g. one for each mode of the first circuit; support a blackout interval during mode changes; support a zoom feature to a subrange of supply voltage disabled with fine-grain histogram buckets; and/or include one or more comparators to detect maximum and/or minimum voltages experienced over a time interval.

公开(公告)号：US20150236705A1

公开(公告)日：2015-08-20

申请号：US14180976

申请日：2014-02-14

Applicant: Apple Inc.

Inventor： Jong-Suk Lee ,  Shih-Chieh R. Wen ,  Toshinari Takayanagi ,  Wei-Han Lien

IPC: H03L7/08 ,  H03K5/00

CPC classification number: H03L7/08 ,  G06F1/08 ,  G06F1/3237 ,  G06F1/324 ,  H03K5/00006 ,  H03L7/10 ,  H03L2207/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D50/20

Abstract: A method and apparatus for achieving fast PLL lock when exiting a low power state is disclosed. In one embodiment, a method includes operating a PLL in a first state in which the PLL is locked to a first frequency. The method further includes programming the PLL to operate in a second state in which the PLL is locked to a second frequency. The programming may occur while the PLL is operating in the first state, and the PLL may continue operating in the first state after programming is complete. Thereafter, the PLL may be transitioned from the first state to a low power state. Upon exiting the low power state, the PLL may transition directly to the second state, locking to the second frequency, without having to transition to the first state or lock to the first frequency.

Abstract translation: 公开了一种在退出低功率状态时实现快速PLL锁定的方法和装置。 在一个实施例中，一种方法包括在PLL锁定到第一频率的第一状态下操作PLL。 该方法还包括对PLL进行编程以在PLL被锁定到第二频率的第二状态下工作。 当PLL处于第一状态时，可能会发生编程，并且编程完成后，PLL可能继续在第一状态下工作。 此后，PLL可以从第一状态转换到低功率状态。 在退出低功率状态时，PLL可以直接转换到第二状态，锁定到第二频率，而不必转换到第一状态或锁定到第一频率。

公开(公告)号：US20140122908A1

公开(公告)日：2014-05-01

申请号：US14149922

申请日：2014-01-08

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Jung Wook Cho ,  Toshinari Takayanagi ,  Timothy J. Millet

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

公开(公告)号：US20190286210A1

公开(公告)日：2019-09-19

申请号：US16363762

申请日：2019-03-25

Applicant: Apple Inc.

Inventor： Toshinari Takayanagi ,  Jung Wook Cho ,  Patrick D. McNamara

IPC: G06F1/324 ,  G06F1/26 ,  G06F1/3296

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

公开(公告)号：US10241560B2

公开(公告)日：2019-03-26

申请号：US15212880

申请日：2016-07-18

Applicant: Apple Inc.

Inventor： Toshinari Takayanagi ,  Jung Wook Cho ,  Patrick D. McNamara

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/324 ,  G06F1/3296

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

公开(公告)号：US20170010646A1

公开(公告)日：2017-01-12

申请号：US15212880

申请日：2016-07-18

Applicant: Apple Inc.

Inventor： Toshinari Takayanagi ,  Jung Wook Cho ,  Patrick D. McNamara

IPC: G06F1/32 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  G06F1/266 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level.

Abstract translation: 一种用于管理当前需求的变化的系统，包括一个或多个处理器，耦合到至少一个处理器的存储器，时钟生成电路，其耦合到存储器并被配置为输出时钟，一个或多个功能块，电源 ，被配置为输出多个电压电平，以及电源管理单元。 功率管理单元可以被配置为将电源输出设置为第一电压电平，然后检测SoC内当前需求即将发生变化的指示。 如果检测到当前需求即将发生变化的指示，则电源管理单元可以被配置为将电源输出调整到第二电压电平。 在确定了当前需求即将发生变化之后，电源管理单元可被配置为将电源输出调整回到第一电压电平。

公开(公告)号：US10859628B2

公开(公告)日：2020-12-08

申请号：US16375344

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

IPC: G01R31/317 ,  G01R19/00 ,  H03M1/12 ,  G01R31/3177

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

公开(公告)号：US08959369B2

公开(公告)日：2015-02-17

申请号：US14149922

申请日：2014-01-08

Applicant: Apple Inc.

Inventor： Josh P. de Cesare ,  Jung Wook Cho ,  Toshinari Takayanagi ,  Timothy J. Millet

IPC: G06F1/00 ,  G06F1/32 ,  G09G3/18 ,  G11C5/14 ,  H04M1/00 ,  G06F1/26

CPC classification number: G06F1/26 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract translation: 在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。 性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。 在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

公开(公告)号：US20140300407A1

公开(公告)日：2014-10-09

申请号：US14308886

申请日：2014-06-19

Applicant: Apple Inc.

Inventor： Toshinari Takayanagi ,  Shingo Suzuki

IPC: H03K17/284

CPC classification number: H03K17/284 ,  H03K17/0412 ,  H03K17/04206 ,  H03K17/164 ,  H03K19/0016 ,  H03K19/00361 ,  Y10T307/858

Abstract: A method an apparatus for a power switch acceleration scheme during wakeup is disclosed. In one embodiment, an integrated circuit includes at least one power gated circuit block. The power gated circuit block includes a virtual voltage node from which a voltage is provided to the circuitry of the block when active. Power switches are coupled between the virtual voltage node and a corresponding global voltage node. When the power gated circuit block is powered on, power switches are activated sequentially. The rate at which power switches are activated is increased as the voltage on the virtual voltage node increases. Sequentially activating the power switches may prevent an excess of current inrush into the power gated circuit block. The increase in the rate at which power switches are activated when the voltage on the virtual voltage node is at least at a certain level may allow for a faster wakeup.

Abstract translation: 公开了一种在唤醒期间用于电源开关加速方案的装置。 在一个实施例中，集成电路包括至少一个电源门控电路块。 电源门控电路块包括一个虚拟电压节点，当有效时，电压被提供给块的电路。 电源开关耦合在虚拟电压节点和相应的全局电压节点之间。 当电源门控电路块通电时，电源开关被顺序激活。 电源开关激活的速率随着虚拟电压节点上的电压的增加而增加。 顺序地激活功率开关可以防止电流涌入电源门控电路块中的过多电流。 当虚拟电压节点上的电压至少处于一定水平时，功率开关被激活的速率的增加可以允许更快的唤醒。

公开(公告)号：US20200319248A1

公开(公告)日：2020-10-08

申请号：US16375344

申请日：2019-04-04

Applicant: Apple Inc.

Inventor： Bibo Li ,  Bo Yang ,  Vijay M. Bettada ,  Matthias Knoth ,  Toshinari Takayanagi

IPC: G01R31/317 ,  G01R19/00 ,  G01R31/3177 ,  H03M1/12

Abstract: An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.