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公开(公告)号：US10511316B2
公开(公告)日：2019-12-17
申请号：US16053455
申请日：2018-08-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Rares Bodnar , Roberto S. Maurino , Christopher Peter Hurrell , Asif Ahmad
Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.
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Patent Agency Ranking
公开(公告)号：US09391628B1
公开(公告)日：2016-07-12
申请号：US14967880
申请日：2015-12-14
Applicant: ANALOG DEVICES GLOBAL
Inventor： Colin G. Lyden , Pasquale Delizia , Sanjay Rajasekhar , Yogesh Jayarman Sharma , Arthur J. Kalb , Marvin L. Shu , Gerard Mora-Puchalt , Roberto S. Maurino
CPC classification number: H03M1/1245 , G11C27/026
Abstract: An input stage to an analog to digital converter (ADC) includes at least one sampling capacitor (SC) for sampling an input signal in acquire phases, a capacitive gain amplifier (CGA) for providing the input signal to the SC, and bandwidth control means. The bandwidth control means is configured to ensure that the SC has a first bandwidth during a first part of an acquire phase and has a second bandwidth during a subsequent, second, part of said acquire phase, the second bandwidth being smaller than the first. In this manner, first, the input signal is sampled at a higher, first, bandwidth allowing to take advantage of using a high-bandwidth CGA to minimize settling error on the SC, and, next, during a second part of the same acquire phase, the input signal is sampled at a lower, second, bandwidth advantageously decreasing noise resulting from the use of a high-bandwidth CGA.
Abstract translation: 模数转换器（ADC）的输入级包括至少一个用于采集相位中的输入信号的采样电容器（SC），用于向SC提供输入信号的电容增益放大器（CGA）以及带宽控制装置 。 带宽控制装置被配置为确保SC在获取阶段的第一部分期间具有第一带宽，并且在所述获取阶段的后续，第二部分期间具有第二带宽，第二带宽小于第一带宽。 以这种方式，首先，以更高的第一带宽对输入信号进行采样，从而可利用使用高带宽CGA来最小化SC上的稳定误差，并且接下来在相同获取阶段的第二部分期间 ，输入信号以较低，第二带宽进行采样，有利于降低使用高带宽CGA导致的噪声。
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公开(公告)号：US20150326193A1
公开(公告)日：2015-11-12
申请号：US14274258
申请日：2014-05-09
Applicant: ANALOG DEVICES GLOBAL
Inventor： Roberto S. Maurino
CPC classification number: H03F3/45076 , H03F1/26 , H03F3/211 , H03F3/393 , H03F3/45183 , H03F3/45475 , H03F2200/234 , H03F2200/411 , H03F2200/555 , H03F2203/45116 , H03F2203/45212 , H03F2203/45366 , H03F2203/45471 , H03F2203/45562 , H03F2203/45644 , H03F2203/45674
Abstract: An amplifier input stage comprising first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal; first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first signal of the input stage differential input signal and a gate of the second n-type transistor is configured to receive the second signal of the input stage differential input signal; a first circuit arranged to provide a first portion of a first bias current to the first node; and a second circuit arranged to draw a second portion of the first bias current from the second node; wherein the first and second portions are determined by a first signal of an amplifier input signal.
Abstract translation: 放大器输入级包括第一和第二p型晶体管，其中第一和第二p型晶体管的源极连接到第一节点，第一p型晶体管的漏极连接到放大器输入端的第一输出端 第二p型晶体管的漏极连接到放大器输入级的第二输出，第一p型晶体管的栅极被配置为接收输入级差分输入信号的第一信号和第 第二p型晶体管被配置为接收输入级差分输入信号的第二信号; 第一和第二n型晶体管，其中第一和第二n型晶体管的源极连接到第二节点，第一n型晶体管的漏极连接到放大器输入级的第三输出端，漏极 第二n型晶体管连接到放大器输入级的第四输出端，第一n型晶体管的栅极被配置为接收输入级差分输入信号的第一信号和第二n型晶体管的栅极 晶体管被配置为接收输入级差分输入信号的第二信号; 第一电路，被布置成向第一节点提供第一偏置电流的第一部分; 以及第二电路，布置成从所述第二节点绘制所述第一偏置电流的第二部分; 其中第一和第二部分由放大器输入信号的第一信号确定。
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公开(公告)号：US09312825B2
公开(公告)日：2016-04-12
申请号：US14274258
申请日：2014-05-09
Applicant: Analog Devices Global
Inventor： Roberto S. Maurino
CPC classification number: H03F3/45076 , H03F1/26 , H03F3/211 , H03F3/393 , H03F3/45183 , H03F3/45475 , H03F2200/234 , H03F2200/411 , H03F2200/555 , H03F2203/45116 , H03F2203/45212 , H03F2203/45366 , H03F2203/45471 , H03F2203/45562 , H03F2203/45644 , H03F2203/45674
Abstract: An amplifier input stage comprising first and second p-type transistors, wherein sources of the first and second p-type transistors are connected to a first node, a drain of the first p-type transistor is connected to a first output of the amplifier input stage, a drain of the second p-type transistor is connected to a second output of the amplifier input stage, a gate of the first p-type transistor is configured to receive a first signal of an input stage differential input signal and a gate of the second p-type transistor is configured to receive a second signal of the input stage differential input signal; first and second n-type transistors, wherein sources of the first and second n-type transistors are connected to a second node, a drain of the first n-type transistor is connected to a third output of the amplifier input stage, a drain of the second n-type transistor is connected to a fourth output of the amplifier input stage, a gate of the first n-type transistor is configured to receive the first signal of the input stage differential input signal and a gate of the second n-type transistor is configured to receive the second signal of the input stage differential input signal; a first circuit arranged to provide a first portion of a first bias current to the first node; and a second circuit arranged to draw a second portion of the first bias current from the second node; wherein the first and second portions are determined by a first signal of an amplifier input signal.
Abstract translation: 放大器输入级包括第一和第二p型晶体管，其中第一和第二p型晶体管的源极连接到第一节点，第一p型晶体管的漏极连接到放大器输入端的第一输出端 第二p型晶体管的漏极连接到放大器输入级的第二输出，第一p型晶体管的栅极被配置为接收输入级差分输入信号的第一信号和第 第二p型晶体管被配置为接收输入级差分输入信号的第二信号; 第一和第二n型晶体管，其中第一和第二n型晶体管的源极连接到第二节点，第一n型晶体管的漏极连接到放大器输入级的第三输出端，漏极 第二n型晶体管连接到放大器输入级的第四输出端，第一n型晶体管的栅极被配置为接收输入级差分输入信号的第一信号和第二n型晶体管的栅极 晶体管被配置为接收输入级差分输入信号的第二信号; 第一电路，被布置成向第一节点提供第一偏置电流的第一部分; 以及第二电路，布置成从所述第二节点绘制所述第一偏置电流的第二部分; 其中第一和第二部分由放大器输入信号的第一信号确定。
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公开(公告)号：US09294037B2
公开(公告)日：2016-03-22
申请号：US14223650
申请日：2014-03-24
Applicant: ANALOG DEVICES GLOBAL
CPC classification number: H03F1/02 , H03F1/0277 , H03F3/45076 , H03F3/45475 , H03F3/45968 , H03F2200/234 , H03F2203/45288
Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.
Abstract translation: 本文提供了用于自动调零放大器的装置和方法。 在某些配置中，自动调零放大器包括至少三个跨导级和被配置为控制跨导级的自动调零序列的自动调零定时控制电路。 自动调零定时控制电路可以错开跨导级的自动调零，使得相对较少量的放大器的放大电路在任何给定的时间与放大器的信号路径相连或断开。 例如，在某些配置中，当在特定时间间隔内自动归零的跨导级之一时，剩余的跨导级可以并行操作以在该时间间隔期间提供放大。
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公开(公告)号：US20150270805A1
公开(公告)日：2015-09-24
申请号：US14223650
申请日：2014-03-24
Applicant: ANALOG DEVICES GLOBAL
CPC classification number: H03F1/02 , H03F1/0277 , H03F3/45076 , H03F3/45475 , H03F3/45968 , H03F2200/234 , H03F2203/45288
Abstract: Apparatus and methods for autozero amplifiers are provided herein. In certain configurations, an autozero amplifier includes at least three transconductance stages and an autozero timing control circuit configured to control an autozero sequence of the transconductance stages. The autozero timing control circuit can stagger autozeroing of the transconductance stages, such that a relatively small amount of the amplifier's amplification circuitry is connected to or disconnected from the amplifier's signal path at any given time. For example, in certain configurations, when one of the transconductance stages in autozeroed over a particular time interval, the remaining transconductance stages can operate in parallel to provide amplification during that time interval.
Abstract translation: 本文提供了用于自动调零放大器的装置和方法。 在某些配置中，自动调零放大器包括至少三个跨导级和被配置为控制跨导级的自动调零序列的自动调零定时控制电路。 自动调零定时控制电路可以错开跨导级的自动调零，使得相对较少量的放大器的放大电路在任何给定的时间与放大器的信号路径相连或断开。 例如，在某些配置中，当在特定时间间隔内自动归零的跨导级之一时，剩余的跨导级可以并行操作以在该时间间隔期间提供放大。
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