公开(公告)号：US20160041941A1

公开(公告)日：2016-02-11

申请号：US14884900

申请日：2015-10-16

Applicant: ANALOG DEVICES, INC.

Inventor： MARTIN KESSLER ,  MIGUEL CHAVEZ ,  LEWIS F. LAHR ,  WILLIAM HOOPER ,  ROBERT ADAMS ,  PETER SEALEY

IPC: G06F13/42 ,  G05B19/418 ,  G05B19/042 ,  H04B3/54 ,  H04L12/403

CPC classification number: G06F13/426 ,  G05B19/0421 ,  G05B19/0423 ,  G05B19/4185 ,  G06F1/26 ,  G06F13/364 ,  G06F13/4282 ,  G06F13/4291 ,  G06F13/4295 ,  H04B3/542 ,  H04B3/548 ,  H04B2203/547 ,  H04L12/4035 ,  H04R29/007 ,  Y02D10/14 ,  Y02D10/151

Abstract: Disclosed herein are two-wire communication systems and applications thereof. In some embodiments, a slave node transceiver for low latency communication may include upstream transceiver circuitry to receive a first signal transmitted over a two-wire bus from an upstream device and to provide a second signal over the two-wire bus to the upstream device; downstream transceiver circuitry to provide a third signal downstream over the two-wire bus toward a downstream device and to receive a fourth signal over the two-wire bus from the downstream device; and clock circuitry to generate a clock signal at the slave node transceiver based on a preamble of a synchronization control frame in the first signal, wherein timing of the receipt and provision of signals over the two-wire bus by the node transceiver is based on the clock signal.

Abstract translation: 这里公开的是两线通信系统及其应用。 在一些实施例中，用于低等待时间通信的从节点收发器可以包括上行收发器电路，用于接收通过双线总线从上游设备发送的第一信号，并通过双线总线向上游设备提供第二信号; 下行收发器电路，用于通过双线总线向下游装置提供第三信号，并通过双线总线从下游装置接收第四信号; 以及时钟电路，用于基于所述第一信号中的同步控制帧的前同步码在所述从节点收发器处产生时钟信号，其中由所述节点收发器通过所述两线总线接收和提供信号的定时基于 时钟信号。

公开(公告)号：US20170222790A1

公开(公告)日：2017-08-03

申请号：US15411801

申请日：2017-01-20

Applicant: Analog Devices, Inc.

Inventor： WILLIAM HOOPER ,  Lewis F. LAHR

IPC: H04L7/00 ,  H04L7/02 ,  H04L12/40

CPC classification number: H04L7/0083 ,  G06F13/30 ,  G06F13/362 ,  H04H60/00 ,  H04J3/0647 ,  H04L7/04 ,  H04L12/40 ,  H04L12/403 ,  H04R5/00 ,  H04R2420/07 ,  H04R2460/03 ,  H04R2499/13

Abstract: Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.