公开(公告)号：US07752383B2

公开(公告)日：2010-07-06

申请号：US11753572

申请日：2007-05-25

Applicant: Chuang Cheng ,  Ching-Chang Chen ,  Satoshi Sugawa ,  Wen-Lin Chang ,  Kai-Hsun Lin ,  Fuja Shone

Inventor： Chuang Cheng ,  Ching-Chang Chen ,  Satoshi Sugawa ,  Wen-Lin Chang ,  Kai-Hsun Lin ,  Fuja Shone

IPC: G06F12/00

CPC classification number: G06F13/4022

Abstract: A method and related system for programming connections between a NAND flash memory controller and a plurality of NAND flash memory modules includes the NAND flash memory controller generating a switch signal and a swap signal according to a condition of one of the plurality of NAND flash memory modules, a remap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the switch signal, and a swap module selectively coupling the plurality of NAND flash memory modules to the NAND flash memory controller according to the swap signal.

Abstract translation: 一种用于在NAND闪速存储器控制器和多个NAND快闪存储器模块之间编程连接的方法和相关系统包括根据多个NAND快闪存储器模块之一的状态产生开关信号和交换信号的NAND闪存控制器 ，根据切换信号将多个NAND快闪存储器模块选择性地耦合到NAND闪速存储器控制器的重映射模块，以及根据交换信号有选择地将多个NAND快闪存储器模块耦合到NAND快闪存储器控制器的交换模块。

公开(公告)号：US5944332A

公开(公告)日：1999-08-31

申请号：US998957

申请日：1997-12-29

Applicant: Hsi Sin Lee ,  Wen Lin Chang

Inventor： Hsi Sin Lee ,  Wen Lin Chang

IPC: B60R3/02 ,  B60R3/00

CPC classification number: B60R3/02

Abstract: A dirt removing running board for automobile includes a cover, a linkage means, a base frame and two steel wires winding to a motor. The linkage means has an upper bar which has a hollow lower portion for housing the upper portion of a lower bar. There is a spring housed in the hollow portion between the upper and lower bars. The lower bar is thus movable up or down to suit different road conditions. The cover is screwed to the chassis of the automobile. The two ends of the linkage means pivotly engage with the cover and base frame respectively to form a substantially Z-shape structure. The motor can release the steel wires to extend the linkage means perpendicular to the cover and the base frame when in use. When the motor rotates in the opposite direction, the steel wires will pull and fold the linkage means and the base frame to the cover for storage. There is a removable dirt removing panel located on the base frame for collecting dirts and muds from the driver and passenger's shoes so that the inside of the automobile may be kept clean.

Abstract translation: 用于汽车的除尘运行板包括一个盖子，一个联动装置，一个基架和两根钢丝绳缠绕到马达上。 连接装置具有上杆，该上杆具有用于容纳下杆的上部的中空下部。 在上下杆之间的中空部分中有一个弹簧。 因此，下条可以上下移动以适应不同的路况。 盖子被拧到汽车的底盘上。 联动装置的两端分别与盖和底架枢转地接合以形成基本上Z形的结构。 在使用时，电机可以释放钢丝，使连接装置垂直于盖板和底座延伸。 当电机沿相反方向旋转时，钢丝绳将拉链和连接装置和基架折叠到盖子上以便储存。 位于基座上的可拆卸的除尘面板用于从驾驶员和乘客鞋上收集污物和泥浆，使得汽车内部可以保持清洁。

公开(公告)号：US20090283600A1

公开(公告)日：2009-11-19

申请号：US12285187

申请日：2008-09-30

Applicant: Wen-Lin Chang ,  Satoshi Sugawa ,  Chuang Cheng ,  Ching-Hu Chen

Inventor： Wen-Lin Chang ,  Satoshi Sugawa ,  Chuang Cheng ,  Ching-Hu Chen

IPC: G06K7/06

CPC classification number: G06F13/385 ,  G06F13/4072

Abstract: A card reader includes a card interface, and one of the pins of the card interface is selected to decide the state of the card interface. The card reader further includes a control circuit to detect the logic state of the selected pin. If the logic state is a first one, the control circuit decides the card interface is enabled; otherwise, if the logic state is a second one, the control circuit decides the card interface is disabled. In some embodiments, a switch is connected between the selected pin and a power supply or a ground terminal, to be switched by a control signal to enable or disable the card interface.

Abstract translation: 读卡器包括卡接口，并且选择卡接口的一个引脚来决定卡接口的状态。 读卡器还包括用于检测所选引脚的逻辑状态的控制电路。 如果逻辑状态是第一个，控制电路决定卡接口被使能; 否则，如果逻辑状态是第二个逻辑状态，则控制电路决定卡接口被禁用。 在一些实施例中，开关连接在所选择的引脚和电源或接地端子之间，以通过控制信号切换以启用或禁用卡接口。

公开(公告)号：US20120286308A1

公开(公告)日：2012-11-15

申请号：US13242452

申请日：2011-09-23

Applicant: Chieh-Lung Lai ,  Wen-Lin Chang ,  Chih-Sheng Hsu ,  Chang-Yueh Chan

Inventor： Chieh-Lung Lai ,  Wen-Lin Chang ,  Chih-Sheng Hsu ,  Chang-Yueh Chan

IPC: H01L33/50 ,  H01L33/52 ,  H01L33/62

CPC classification number: H01L33/507 ,  H01L25/0753 ,  H01L33/486 ,  H01L33/58 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2933/0041 ,  H01L2924/00014

Abstract: An LED package structure and a method of fabricating the same. The LED package structure includes: a package unit including a submount with a cavity, and a light emitting chip disposed in the cavity; a first light-pervious element disposed in the cavity; a multi-layered dam structure concentrically disposed on the first light-pervious element or around a rim of the cavity; a first light-pervious packaging material filled in the dam structure; and a second light-pervious element that combines with the dam structure. Accordingly, the multi-layered dam structure provides an advantage of eliminating gaps and overcomes the problem resulting from the uneven thickness of the first light-pervious packaging material used in the prior technique, thereby ensuring high illumination efficiency and enhanced airtightness.

Abstract translation: 一种LED封装结构及其制造方法。 LED封装结构包括：封装单元，其包括具有空腔的基座和设置在空腔中的发光芯片; 设置在所述空腔中的第一透光元件; 同心地设置在所述第一透光元件上或围绕所述空腔的边缘的多层坝结构; 填充在坝体结构中的第一透光性包装材料; 和与坝结构相结合的第二透光元件。 因此，多层坝结构提供了消除间隙的优点，并且克服了由于现有技术中使用的第一透光性包装材料的厚度不均匀导致的问题，从而确保了高的照明效率和增强的气密性。

公开(公告)号：US20090043945A1

公开(公告)日：2009-02-12

申请号：US12120453

申请日：2008-05-14

Applicant: Chuang Cheng ,  Satashi Sugawa ,  Chih-Wei Tsai ,  Wen-Lin Chang ,  Fu-Ja Shone

Inventor： Chuang Cheng ,  Satashi Sugawa ,  Chih-Wei Tsai ,  Wen-Lin Chang ,  Fu-Ja Shone

IPC: G06F12/00

CPC classification number: G06F13/4239 ,  G11C7/1042

Abstract: A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced.

Abstract translation: 提供一种非易失性存储器系统和从其读取数据的方法。 数据包括第一子数据和第二子数据。 非易失性存储器系统包括分别存储两个子数据的第一存储单元和第二存储单元。 第一存储单元从控制器读取第一命令，并且根据第一命令临时存储第一子数据作为第一临时子数据。 第二存储单元从控制器读取第二命令，并且根据第二命令临时存储第二子数据作为第二临时子数据。 从第一存储单元读取第一临时子数据。 然后，第一存储单元从控制器读取第三命令。 在读取第三命令的同时，也从第二存储单元读取第二临时子数据。 从非易失性存储器系统读取数据的时间减少了。

公开(公告)号：US07145802B2

公开(公告)日：2006-12-05

申请号：US10929682

申请日：2004-08-31

Applicant: Fuja Shone ,  I-Long Lee ,  Yi-Ching Liu ,  Hsin-Chien Chen ,  Wen-Lin Chang

Inventor： Fuja Shone ,  I-Long Lee ,  Yi-Ching Liu ,  Hsin-Chien Chen ,  Wen-Lin Chang

IPC: G11C11/34

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115

Abstract: A method for programming a split gate memory cell comprises the following steps. First, a split gate memory cell formed on a semiconductor substrate of a first conductive type, e.g., p-type, is provided. The split gate memory cell has two bitlines of a second conductive type, e.g., n-type, a select gate, a floating gate, a wordline and a dielectric layer deposited between the floating gate and the semiconductor substrate, wherein the select gate and floating gate are transversely disposed between the two bitlines, the wordline is above the select gate and floating gate. Second, a positive voltage is applied to the wordline so as to turn on the floating gate, and a negative voltage is applied to the bitline next to the floating gate, whereby a bias voltage across the tunnel dielectric layer is generated for programming, that is, the so called F-N programming.

公开(公告)号：US20060044876A1

公开(公告)日：2006-03-02

申请号：US10929682

申请日：2004-08-31

Applicant: Fuja Shone ,  I-Long Lee ,  Yi-Ching Liu ,  Hsin-Chien Chen ,  Wen-Lin Chang

Inventor： Fuja Shone ,  I-Long Lee ,  Yi-Ching Liu ,  Hsin-Chien Chen ,  Wen-Lin Chang

IPC: G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/0425 ,  H01L27/115

Abstract: A method for programming a split gate memory cell comprises the following steps. First, a split gate memory cell formed on a semiconductor substrate of a first conductive type, e.g., p-type, is provided. The split gate memory cell has two bitlines of a second conductive type, e.g., n-type, a select gate, a floating gate, a wordline and a dielectric layer deposited between the floating gate and the semiconductor substrate, wherein the select gate and floating gate are transversely disposed between the two bitlines, the wordline is above the select gate and floating gate. Second, a positive voltage is applied to the wordline so as to turn on the floating gate, and a negative voltage is applied to the bitline next to the floating gate, whereby a bias voltage across the tunnel dielectric layer is generated for programming, that is, the so called F-N programming.

Abstract translation: 用于编程分离门存储器单元的方法包括以下步骤。 首先，提供形成在第一导电类型例如p型的半导体衬底上的分离栅极存储单元。 分离栅极存储单元具有沉积在浮置栅极和半导体衬底之间的第二导电类型的两个位线，例如n型，选择栅极，浮置栅极，字线和介电层，其中选择栅极和浮置栅极 栅极横向设置在两个位线之间，字线位于选择栅极和浮动栅极之上。 第二，将正电压施加到字线以便导通浮置栅极，并且将负电压施加到浮置栅极旁边的位线，由此产生跨隧道介电层的偏置电压用于编程，即， ，所谓的FN编程。

公开(公告)号：US08166228B2

公开(公告)日：2012-04-24

申请号：US12120453

申请日：2008-05-14

Applicant: Chuang Cheng ,  Satashi Sugawa ,  Chih-Wei Tsai ,  Wen-Lin Chang ,  Fu-Ja Shone

Inventor： Chuang Cheng ,  Satashi Sugawa ,  Chih-Wei Tsai ,  Wen-Lin Chang ,  Fu-Ja Shone

IPC: G06F12/00

CPC classification number: G06F13/4239 ,  G11C7/1042

Abstract: A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced.

Abstract translation: 提供一种非易失性存储器系统和从其读取数据的方法。 数据包括第一子数据和第二子数据。 非易失性存储器系统包括分别存储两个子数据的第一存储单元和第二存储单元。 第一存储单元从控制器读取第一命令，并且根据第一命令临时存储第一子数据作为第一临时子数据。 第二存储单元从控制器读取第二命令，并且根据第二命令临时存储第二子数据作为第二临时子数据。 从第一存储单元读取第一临时子数据。 然后，第一存储单元从控制器读取第三命令。 在读取第三命令的同时，也从第二存储单元读取第二临时子数据。 从非易失性存储器系统读取数据的时间减少了。