Invention Application
- Patent Title: DUTY CYCLE CORRECTION SYSTEM AND LOW DROPOUT (LDO) REGULATOR BASED DELAY-LOCKED LOOP (DLL)
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Application No.: US17357456Application Date: 2021-06-24
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Publication No.: US20210320652A1Publication Date: 2021-10-14
- Inventor: Aaron Martin , Roger Cheng , Hari Venkatramani , Navneet Dour , Mozhgan Mansuri , Bryan Casper , Frank O'Mahony , Ganesh Balamurugan , Ajay Balankutty , Kuan Zhou , Sridhar Tirumalai , Krishnamurthy Venkataramana , Alex Thomas , Quoc Nguyen
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Main IPC: H03K5/156
- IPC: H03K5/156 ; H03L7/081 ; G11C7/22 ; G06F1/08 ; G11C7/10

Abstract:
An apparatus is provided, where the apparatus includes a plurality of components; a first circuitry to generate a clock signal, and to supply the clock signal to the plurality of components; a second circuitry to estimate, for each of two or more components of the plurality of components, a corresponding duty cycle of the clock signal received at the corresponding component, wherein two or more duty cycles corresponding to the two or more components are determined; a third circuitry to determine an average of the two or more duty cycles; and a fourth circuitry to correct a duty cycle of the clock signal generated by the first circuitry, based at least in part on the average.
Public/Granted literature
- US11722128B2 Duty cycle correction system and low dropout (LDO) regulator based delay-locked loop (DLL) Public/Granted day:2023-08-08
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