- 专利标题: Pillared Cavity Down MIS-SIP
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申请号: US17345174申请日: 2021-06-11
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公开(公告)号: US20210305167A1公开(公告)日: 2021-09-30
- 发明人: Ernesto Gutierrez, III , Jesus Mennen Belonio , Eric Hu , Melvin Martin , Jerry Li , Francisco Vergara Cadacio
- 申请人: Dialog Semiconductor (UK) Limited
- 申请人地址: GB London
- 专利权人: Dialog Semiconductor (UK) Limited
- 当前专利权人: Dialog Semiconductor (UK) Limited
- 当前专利权人地址: GB London
- 主分类号: H01L23/538
- IPC分类号: H01L23/538 ; H01L21/48 ; H01L25/16 ; H01L23/00 ; H01L23/498 ; H01L23/31 ; H01L25/065
摘要:
A substrate is provided having a top side and a bottom side, having redistribution layers therein, having at least one copper pillar connected to the redistribution layers on the top side and at least one copper pillar connected to the redistribution layers on the bottom side, and having at least one cavity extending partially into the bottom side of the substrate. At least one passive component is mounted onto the copper pillar on the top side and embedded in a molding compound. At least one silicon die is mounted in the cavity wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers. At least one solder ball is mounted on the at least one copper pillar on the bottom side of the substrate to provide package output.
公开/授权文献
- US11532489B2 Pillared cavity down MIS-SiP 公开/授权日:2022-12-20
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