Invention Application
- Patent Title: Pillared Cavity Down MIS-SIP
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Application No.: US17345174Application Date: 2021-06-11
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Publication No.: US20210305167A1Publication Date: 2021-09-30
- Inventor: Ernesto Gutierrez, III , Jesus Mennen Belonio , Eric Hu , Melvin Martin , Jerry Li , Francisco Vergara Cadacio
- Applicant: Dialog Semiconductor (UK) Limited
- Applicant Address: GB London
- Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee: Dialog Semiconductor (UK) Limited
- Current Assignee Address: GB London
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L21/48 ; H01L25/16 ; H01L23/00 ; H01L23/498 ; H01L23/31 ; H01L25/065

Abstract:
A substrate is provided having a top side and a bottom side, having redistribution layers therein, having at least one copper pillar connected to the redistribution layers on the top side and at least one copper pillar connected to the redistribution layers on the bottom side, and having at least one cavity extending partially into the bottom side of the substrate. At least one passive component is mounted onto the copper pillar on the top side and embedded in a molding compound. At least one silicon die is mounted in the cavity wherein electrical connections are made between the at least one silicon die and the at least one passive component through the redistribution layers. At least one solder ball is mounted on the at least one copper pillar on the bottom side of the substrate to provide package output.
Public/Granted literature
- US11532489B2 Pillared cavity down MIS-SiP Public/Granted day:2022-12-20
Information query
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