Invention Grant
- Patent Title: Apparatus and method for store pairing with reduced hardware requirements
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Application No.: US16833596Application Date: 2020-03-28
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Publication No.: US11544062B2Publication Date: 2023-01-03
- Inventor: Raanan Sade , Igor Yanover , Stanislav Shwartsman , Muhammad Taher , David Zysman , Liron Zur , Yiftach Gilad
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/38 ; G06F9/48 ; G06F9/50

Abstract:
An apparatus and method for pairing store operations. For example, one embodiment of a processor comprises: a grouping eligibility checker to evaluate a plurality of store instructions based on a set of grouping rules to determine whether two or more of the plurality of store instructions are eligible for grouping; and a dispatcher to simultaneously dispatch a first group of store instructions of the plurality of store instructions determined to be eligible for grouping by the grouping eligibility checker.
Public/Granted literature
- US20210096860A1 Apparatus and Method for Store Pairing with Reduced Hardware Requirements Public/Granted day:2021-04-01
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