- 专利标题： Reduction of gate-drain capacitance
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申请号： US16888537申请日： 2020-05-29
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公开(公告)号： US11532626B2公开(公告)日： 2022-12-20
- 发明人: Jung-Hung Chang , Lo-Heng Chang , Zhi-Chang Lin , Shih-Cheng Chen , Kuo-Cheng Chiang , Chih-Hao Wang
- 申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 申请人地址： TW Hsin-Chu
- 专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人： Taiwan Semiconductor Manufacturing Co., Ltd.
- 当前专利权人地址： TW Hsin-Chu
- 代理机构： Haynes and Boone, LLP
- 主分类号： H01L29/78
- IPC分类号： H01L29/78 ; H01L27/092 ; H01L21/02 ; H01L21/8238 ; H01L29/08 ; H01L29/66 ; H01L29/10
摘要：
A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
公开/授权文献
- US20210375864A1 REDUCTION OF GATE-DRAIN CAPACITANCE 公开/授权日：2021-12-02
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