The present technology relates to an error correction circuit. According to the present technology, an error correction circuit performing error correction encoding on a plurality of messages to be stored in a memory device includes a first error correction encoder and a second error correction encoder. The first error correction encoder generates a plurality of codewords by performing first error correcting encoding on each of the plurality of messages. The second error correction encoder performs a second error correction encoding operation by performing an exclusive OR operation on symbols of an identical column layer within the codewords. The second error correction encoder determines a data unit as a target of the second error correction encoding operation based on a use period of the memory device.