A memory includes: a first data bus; a second data bus; and a plurality of bank groups. The bank groups output read data by alternately using the first data bus and the second data bus during read operations of the bank groups. One of the plurality of bank groups transfer read data to the first data bus during a read operation based on an odd-numbered read command. Further, one of the plurality of bank groups transfer transfer one of the plurality of bank groups read data to the second data bus during a read operation based on an even-numbered read command.