- 专利标题: Calibration of skew between clock phases
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申请号: US17245711申请日: 2021-04-30
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公开(公告)号: US11416021B2公开(公告)日: 2022-08-16
- 发明人: Ani Xavier , Jagannathan Venkataraman , Raviteja Velisetti
- 申请人: Texas Instruments Incorporated
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 John R. Pessetto; Charles A. Brill; Frank D. Cimino
- 优先权: IN202041055927 20201222
- 主分类号: G06F1/10
- IPC分类号: G06F1/10 ; H03L7/081 ; H03K19/20
摘要:
A first logic gate has a first input coupled to a first circuit input or a second circuit input, a second input selectively coupled to a third circuit input or a fourth circuit input, and a first output. The first output has a signal with a duty cycle that is a function of a phase difference between a first signal on the first input and a second signal on the second input. A second logic gate has a third input coupled to the third circuit input or the fourth circuit input, a fourth input coupled to the second circuit input or the fourth circuit input, and a second output. The second output has a signal with a duty cycle that is a function of a phase difference between a third signal on the third input and a fourth signal on the fourth input.
公开/授权文献
- US20220197330A1 CALIBRATION OF SKEW BETWEEN CLOCK PHASES 公开/授权日:2022-06-23
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