公开(公告)号：US11416021B2

公开(公告)日：2022-08-16

申请号：US17245711

申请日：2021-04-30

申请人： Texas Instruments Incorporated

发明人： Ani Xavier ,  Jagannathan Venkataraman ,  Raviteja Velisetti

IPC分类号： G06F1/10 ,  H03L7/081 ,  H03K19/20

摘要： A first logic gate has a first input coupled to a first circuit input or a second circuit input, a second input selectively coupled to a third circuit input or a fourth circuit input, and a first output. The first output has a signal with a duty cycle that is a function of a phase difference between a first signal on the first input and a second signal on the second input. A second logic gate has a third input coupled to the third circuit input or the fourth circuit input, a fourth input coupled to the second circuit input or the fourth circuit input, and a second output. The second output has a signal with a duty cycle that is a function of a phase difference between a third signal on the third input and a fourth signal on the fourth input.