Invention Grant
- Patent Title: Pooled DRAM system enabled by monolithic in-package optical I/O
-
Application No.: US17175678Application Date: 2021-02-14
-
Publication No.: US11233580B2Publication Date: 2022-01-25
- Inventor: Roy Edward Meade , Vladimir Stojanovic , Chen Sun , Mark Wade , Hugo Saleh , Charles Wuischpard
- Applicant: Ayar Labs, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Ayar Labs, Inc.
- Current Assignee: Ayar Labs, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Penilla IP, APC
- Main IPC: G11C5/04
- IPC: G11C5/04 ; G11C5/06 ; G11C11/42 ; H04B10/80 ; H04B10/516

Abstract:
A computer memory system includes an electro-optical chip, an electrical fanout chip electrically connected to an electrical interface of the electro-optical chip, and at least one dual in-line memory module (DIMM) slot electrically connected to the electrical fanout chip. A photonic interface of the electro-optical chip is optically connected to an optical link. The electro-optical chip includes at least one optical macro that converts outgoing electrical data signals into outgoing optical data signals for transmission through the optical link. The optical macro also converts incoming optical data signals from the optical link into incoming electrical data signals and transmits the incoming electrical data signals to the electrical fanout chip. The electrical fanout chip directs bi-directional electrical data communication between the electro-optical chip and a dynamic random access memory (DRAM) DIMM corresponding to the at least one DIMM slot.
Public/Granted literature
- US20210257021A1 Pooled DRAM System Enabled by Monolithic In-Package Optical I/O Public/Granted day:2021-08-19
Information query