- 专利标题: Method of fabricating an interposer
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申请号: US15586716申请日: 2017-05-04
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公开(公告)号: US10535534B2公开(公告)日: 2020-01-14
- 发明人: Un-Byoung Kang , Tae-Je Cho , Hyuek-Jae Lee , Cha-Jea Jo
- 申请人: SAMSUNG ELECTRONICS CO., LTD.
- 申请人地址: KR Suwon-si, Gyeonggi-Do
- 专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人: SAMSUNG ELECTRONICS CO., LTD.
- 当前专利权人地址: KR Suwon-si, Gyeonggi-Do
- 代理机构: F. Chau & Associates, LLC
- 优先权: KR10-2016-0058234 20160512
- 主分类号: H01L21/48
- IPC分类号: H01L21/48 ; H05K3/46 ; C23C18/00 ; H01L23/433 ; H01L23/498 ; B05D1/00 ; B05D1/32 ; B05D1/38 ; B05D3/02 ; B05D7/00 ; C23C14/02 ; C23C14/04 ; C23C14/06 ; C23C14/20 ; C23C14/34 ; C23C14/58 ; C23C18/38 ; H01L23/00 ; H01L25/03 ; H01L23/473 ; H01L23/538 ; H01L25/065
摘要:
A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat. According to the method, no undercut occurs under a conductive structure and there are no bubbles between adjacent conductive structures, thus device reliability is enhanced and pattern accuracy is realized.
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