Invention Grant
- Patent Title: Memory system
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Application No.: US15402522Application Date: 2017-01-10
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Publication No.: US10073624B2Publication Date: 2018-09-11
- Inventor: Shinken Okamoto
- Applicant: TOSHIBA MEMORY CORPORATION
- Applicant Address: JP Minato-ku
- Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee: TOSHIBA MEMORY CORPORATION
- Current Assignee Address: JP Minato-ku
- Agency: Oblon, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2010-027944 20100210
- Main IPC: G11C16/14
- IPC: G11C16/14 ; G11C16/16 ; G11C29/04 ; G06F3/06 ; G06F12/02 ; G06F11/10 ; G06F11/30 ; G11C29/50 ; G06F11/32 ; G11C16/34 ; G11C29/52

Abstract:
According to the embodiments, a memory system includes a nonvolatile semiconductor memory and a writing-loop-count monitoring unit that monitors a loop count of an applied voltage to the nonvolatile semiconductor memory required for data writing of the nonvolatile semiconductor memory as a writing loop count. Moreover, the memory system includes a management table for managing the writing loop count in block unit that is a unit of data erasing and a life managing unit that determines a degraded state of the nonvolatile semiconductor memory based on the management table.
Public/Granted literature
- US20170123673A1 MEMORY SYSTEM Public/Granted day:2017-05-04
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