公开(公告)号：US20240179891A1

公开(公告)日：2024-05-30

申请号：US18072348

申请日：2022-11-30

申请人： Winbond Electronics Corp.

发明人： Hung-Yu WEI

IPC分类号： H01L27/108

CPC分类号： H01L27/10823 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor structure is provided. The semiconductor structure includes a substrate, an isolation feature, a word line and a doped region. The substrate has an active region. The isolation feature is disposed in the substrate to define the active region. The word line is buried in the substrate and extends across the active region and the isolation feature. The word line includes a first conductive structure and a second conductive structure disposed on the first conductive structure. The doped region is disposed in the active region and adjacent to the word line, wherein a top surface of the first conductive structure is below a bottom surface of the doped region.

公开(公告)号：US11991875B2

公开(公告)日：2024-05-21

申请号：US17463926

申请日：2021-09-01

申请人： Winbond Electronics Corp.

发明人： Chien-Ming Lu ,  Po-Han Wu

IPC分类号： H01L27/108 ,  H10B12/00

CPC分类号： H10B12/315 ,  H10B12/0335 ,  H10B12/34 ,  H10B12/482

摘要： A semiconductor memory structure includes a substrate, a bit line disposed on the substrate, a dielectric liner disposed on a side of the bit line, and a capacitor contact and a filler disposed on the substrate. The bit line extends in a first direction. The dielectric liner includes a first nitride liner disposed on a sidewall of the bit line, an oxide liner disposed on a sidewall of the first nitride liner, and a second nitride liner disposed on a sidewall of the oxide liner. In a second direction perpendicular to the first direction, the capacitor contact is spaced apart from the bit line by the first nitride liner, the oxide liner, and the second nitride liner, and the width of the filler is greater than the width of the capacitor contact. A method for forming the semiconductor memory structure is also provided.

公开(公告)号：US11984399B2

公开(公告)日：2024-05-14

申请号：US17661334

申请日：2022-04-29

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Xiang Liu

IPC分类号： H01L23/528 ,  H01L27/108 ,  H10B12/00

CPC分类号： H01L23/528 ,  H10B12/00

摘要： Embodiments of the present application relate to the field of semiconductor manufacturing technologies, in particular to a semiconductor structure and a mask plate structure. The semiconductor structure includes a substrate, where the substrate is provided therein with active areas and a plurality of bit line structures arranged at intervals in parallel in the substrate. A plurality of word line structures are arranged at intervals in parallel in the substrate. The word line structures and the bit line structures intersect to define a plurality of grids arranged in an array on the substrate. Capacitor plugs are located in the grids. Projection of each of the capacitor plugs on the substrate covers a part of one of the active areas. Cross sections of the capacitor plugs are arcuate in a cross section parallel to a surface of the substrate.

公开(公告)号：US20240147703A1

公开(公告)日：2024-05-02

申请号：US17978336

申请日：2022-11-01

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L27/108

CPC分类号： H01L27/10888 ,  H01L27/10823

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a first contact positioned on the substrate; a first assistance feature including: a bottom portion positioned in the first contact, and a capping portion positioned on the bottom portion and on a top surface of the first contact; a second contact positioned on the substrate and separated from the first contact; and a second assistance feature positioned on the second contact. The first assistance feature and the second assistance feature include germanium or silicon germanium.

公开(公告)号：US20240130102A1

公开(公告)日：2024-04-18

申请号：US17956127

申请日：2022-09-29

申请人： NANYA TECHNOLOGY CORPORATION

发明人： TSE-YAO HUANG

IPC分类号： H01L27/108

CPC分类号： H01L27/10894 ,  H01L27/10823 ,  H01L27/10897

摘要： The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate including an array area and a peripheral area; and a peripheral gate structure including: a peripheral gate dielectric layer inwardly positioned in the peripheral area of the substrate and including a U-shaped cross-sectional profile; a peripheral gate conductor including a bottom portion positioned on the peripheral gate dielectric layer and a neck portion positioned on the bottom portion; and a peripheral gate capping layer positioned on the peripheral gate dielectric layer and the bottom portion, and surrounding the neck portion. A top surface of the peripheral gate capping layer and a top surface of the neck portion are substantially coplanar.

公开(公告)号：US11950405B2

公开(公告)日：2024-04-02

申请号：US17752921

申请日：2022-05-25

申请人： Samsung Electronics Co., Ltd.

发明人： Yong-Hoon Son

IPC分类号： H01L27/108 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B12/00

CPC分类号： H10B12/30 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482

摘要： Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory devices may include a plurality of layers sequentially stacked on a substrate in a vertical direction, each of the plurality of layers including a bit line extending in a first direction and a semiconductor pattern extending from the bit line in a second direction traversing the first direction, a gate electrode extending through the plurality of layers and including a vertical portion extending through the semiconductor patterns and a first horizontal portion extending from the vertical portion and facing a first surface of one of the semiconductor patterns, and a data storing element electrically connected to the one of the semiconductor patterns. The data storing element includes a first electrode electrically connected to the one of the semiconductor patterns, a second electrode on the first electrode, and a dielectric layer between the first and second electrodes.

公开(公告)号：US20240098965A1

公开(公告)日：2024-03-21

申请号：US17933589

申请日：2022-09-20

申请人： Intel Corporation

发明人： Abhishek A. Sharma ,  Tahir Ghani ,  Wilfred Gomes ,  Anand S. Murthy ,  Pushkar Sharad Ranade ,  Sagar Suthram

IPC分类号： H01L27/108 ,  G11C5/06 ,  G11C5/10 ,  H01L23/48 ,  H01L25/065 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/11514

CPC分类号： H01L27/10876 ,  G11C5/063 ,  G11C5/10 ,  H01L23/481 ,  H01L25/0655 ,  H01L27/10808 ,  H01L27/10823 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/11507 ,  H01L27/11509 ,  H01L27/11514 ,  H01L27/10826 ,  H01L27/10879

摘要： Hybrid manufacturing of access transistors for memory, presented herein, explores how IC components fabricated by different manufacturers may be combined in an IC device to achieve advantages in terms of, e.g., performance, density, number of active memory layers, fabrication approaches, and so on. In one aspect, an IC device may include a support, a first circuit over a first portion of the support, a second circuit over a second portion of the support, a scribe line between the first circuit and the second circuit, and one or more electrical traces extending over the scribe line. In another aspect, an IC device may include a support, a memory array, comprising a first circuit over a first portion of the support and one or more layers of capacitors over the first circuit, and a second circuit over a second portion of the support.

公开(公告)号：US20240090206A1

公开(公告)日：2024-03-14

申请号：US17931430

申请日：2022-09-12

申请人： Micron Technology, Inc.

发明人： Yoshikazu Moriwaki

IPC分类号： H01L27/108

CPC分类号： H01L27/10897

摘要： A microelectronic device is disclosed, comprising a base structure comprising: active regions individually comprising semiconductor material; and isolation regions horizontally alternating with the active regions and individually comprising insulative material; a transistor structure comprising: a channel within one of the active regions of the base structure and horizontally interposed between two of the isolation regions; a gate dielectric structure including a high-k material above the channel; a gate electrode stack on the gate dielectric structure and comprising: diffusion prevention material on the gate dielectric structure and partially horizontally overlapping the channel, an opening in the diffusion prevention material horizontally centered about a horizontal centerline of the channel and having a smaller horizontal dimension than the channel; a conductive material comprising lanthanum on the diffusion prevention material and substantially filling the opening.

公开(公告)号：US20240090197A1

公开(公告)日：2024-03-14

申请号：US17931717

申请日：2022-09-13

申请人： MICRON TECHNOLOGY, INC.

发明人： Harutaka Honda ,  SHOGO OMIYA ,  SHOKO NORIFUSA ,  HIDEKAZU NOBUTO

IPC分类号： H01L27/108

CPC分类号： H01L27/10808 ,  H01L27/10852 ,  H01L27/10894 ,  H01L27/10897

摘要： An apparatus includes: a plurality of capacitors each including first and second conductive portions and a dielectric portion therebetween; a first conductive structure containing the plurality of capacitors therein, and electrically coupled to the second conductive portions of the plurality of capacitors; a second conductive structure on a top surface of the first conductive structure; and a third conductive structure on a top surface of the second conductive structure.

公开(公告)号：US11917813B2

公开(公告)日：2024-02-27

申请号：US17528617

申请日：2021-11-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Ping Hsu

IPC分类号： H01L27/108 ,  H10B12/00

CPC分类号： H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34

摘要： The present disclosure provides a dynamic random access memory (DRAM) array. The memory array includes a semiconductor substrate, an isolation structure and contact enhancement sidewall spacers. The semiconductor substrate has a trench defining laterally separate active areas formed of surface regions of the semiconductor substrate. Top surfaces of a first group of the active areas are recessed with respect to top surfaces of a second group of the active areas. The isolation structure is filled in the trench and in lateral contact with bottom portions of the active areas. The contact enhancement sidewall spacers laterally surround top portions of the active areas, respectively.