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公开(公告)号：US4740878A
公开(公告)日：1988-04-26
申请号：US059539
申请日：1987-06-08
Applicant: Nick G. Carter , Douglas D. Myron
Inventor： Nick G. Carter , Douglas D. Myron
Abstract: A DC power supply provides plural output voltages with respect to a common reference potential by splitting a DC input voltage potential. The input voltage is equally split into dual voltages by the embodiment described. A buffer circuit is provided between a voltage divider network and an output circuit stage coupled to the load. The buffer circuit operates to maintain a reference voltage node in the output stage at a potential substantially equal to the potential at the common node of the voltage divider network. The split voltages appear as independent power supplies to the load coupled to the power supply.
Abstract translation: DC电源通过分割DC输入电压电位而相对于公共参考电位提供多个输出电压。 通过所描述的实施例，输入电压被等分成双电压。 在分压器网络和耦合到负载的输出电路级之间提供缓冲电路。 缓冲电路用于将输出级中的参考电压节点保持在与分压器网络的公共节点处的电位基本相等的电位。 分流电压显示为耦合到电源的负载的独立电源。
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公开(公告)号：US4555655A
公开(公告)日：1985-11-26
申请号：US592857
申请日：1984-03-23
Applicant: Tatsuo Tanaka
Inventor： Tatsuo Tanaka
Abstract: A charging/discharging circuit is formed of transistors Q1, Q2; resistors R1-R4; and a capacitor C. The series resistors R1, R2 are connected between the power supply line +Vcc and the circuit ground. The series resistors R3, R4 are connected between the line +Vcc and the circuit ground. The collector of NPN transistor Q1 is connected to +Vcc, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. The collector of PNP transistor Q1 is connected to the circuit ground, the base thereof is connected to the junction between R3 and R4, and the emitter thereof is coupled to the junction between R1 and R2. Capacitor C is connected in parallel to R2. The charged voltage of C is used as a reference potential VR for another linear circuit. Suppose that R1=R2, R3=R4 and +Vcc=10 V. When +Vcc rises from 0 V to 10 V but VR does not reach to 5 V, Q1 is forwardly biased so that C is quickly charged by the emitter current of Q1. When +Vcc falls from 10 V to 0 V but VR does not reach 0 V, Q2 is forwardly biased so that C is quickly discharged by the emitter current of Q2. When VR=5 V (stationary state), Q1 and Q2 are both cut-off, so that only small currents flow through the series circuits of R1, R2 and R3, R4. The time constant of (R1.vertline..vertline.R2).C can be made large so that VR is free from ripples of +Vcc.
Abstract translation: 充电/放电电路由晶体管Q1，Q2形成; 电阻R1-R4; 和电容器C.串联电阻器R1，R2连接在电源线+ Vcc和电路接地之间。 串联电阻R3，R4连接在线路+ Vcc和电路接地之间。 NPN晶体管Q1的集电极连接到+ Vcc，其基极连接到R3和R4之间的结，其发射极耦合到R1和R2之间的连接处。 PNP晶体管Q1的集电极连接到电路地，其基极连接到R3和R4之间的结，其发射极耦合到R1和R2之间的连接处。 电容器C与R2并联连接。 C的充电电压用作另一线性电路的基准电位VR。 假设R1 = R2，R3 = R4和+ Vcc = 10V。当+ Vcc从0V升至10V但VR不达到5V时，Q1被正向偏置，使得C被发射极电流快速充电 Q1。 当+ Vcc从10V下降到0V而VR不达到0V时，Q2被向前偏置，使得C被Q2的发射极电流快速放电。 当VR = 5 V（静止状态）时，Q1和Q2都截止，只有小电流流过R1，R2和R3，R4的串联电路。 （R1||R2）.C的时间常数可以变大，使得VR没有+ Vcc的波纹。
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公开(公告)号：US4459538A
公开(公告)日：1984-07-10
申请号：US390874
申请日：1982-06-22
Applicant: Youichi Arai , Masayuki Takagi
Inventor： Youichi Arai , Masayuki Takagi
CPC classification number: G05F1/585
Abstract: A power supply circuit which comprises a first power source terminal for applying a plus voltage and a second power source terminal for applying a minus voltage. A first transistor is inserted between the first power source terminal and a load. A second transistor is inserted between a base of the first transistor and a ground potential and is controlled by the voltages applied to the first and second power source terminals. A capacitor is connected to the second power source and ground potential. A sequence of applying or cutting-off voltages to be applied to the load is predetermined even when a sequence of applying or cutting-off the voltages from said first and second power source terminals becomes erratic.
Abstract translation: 一种电源电路，包括用于施加正电压的第一电源端子和用于施加负电压的第二电源端子。 第一晶体管插在第一电源端子和负载之间。 第二晶体管被插入在第一晶体管的基极和接地电位之间，并且被施加到第一和第二电源端子的电压控制。 电容器连接到第二电源和地电位。 即使当施加或切断来自所述第一和第二电源端子的电压的顺序变得不稳定时，施加或切断施加到负载的电压的顺序是预定的。
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公开(公告)号：US3659186A
公开(公告)日：1972-04-25
申请号：US3659186D
申请日：1969-08-28
Applicant: HITACHI LTD , DENRYOKU CHUO KENKYUJO
Inventor： MACHIDA TAKEHIKO , YOSHIDA YUKIO , IWATA KOJI , YOKOYAMA KENJIRO
Abstract: A current from a power transmission line is smoothed by a filter and then compared with a set value to detect and control the transmission current when the transmission current is in the neighborhood of the setpoint. Whereas, the current is directly detected and controlled to the set value without intervening the filter when the deviation rapidly increases.
Abstract translation: 来自电力传输线的电流被滤波器平滑，然后与设定值进行比较，以在传输电流处于设定点附近时检测和控制传输电流。 而当偏差迅速增加时，电流被直接检测并控制到设定值，而不会中断滤波器。
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公开(公告)号：US3581104A
公开(公告)日：1971-05-25
申请号：US3581104D
申请日：1970-03-05
Applicant: HORNISCHFEGER CORP
Inventor： THEW DONALD G
CPC classification number: G05F1/585 , H03F3/04 , Y10T307/281 , Y10T307/422 , Y10T307/445
Abstract: A voltage splitter circuit provides a terminal voltage equal to half the voltage impressed across a pair of voltage busses. The voltage at the intermediate terminal may be used to provide two equal, but opposite, voltages between the intermediate terminal and each of the busses. The intermediate terminal is located between the output circuits of two complementary transistors connected across the busses. The transistors are operated by an amplifier driven by a voltage divider. A feedback circuit exists between the intermediate terminal and the input of the amplifier to stabilize the circuit.
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Patent Agency Ranking
公开(公告)号：US3275927A
公开(公告)日：1966-09-27
申请号：US17985162
申请日：1962-03-15
Applicant: FORBRO DESIGN CORP
Inventor： KENNETH KUPFERBERG
IPC: G05F1/585
CPC classification number: G05F1/585
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公开(公告)号：US11429129B2
公开(公告)日：2022-08-30
申请号：US15930817
申请日：2020-05-13
Applicant: Sensata Technologies, Inc.
Inventor： Neil J. Howard , Davide Bianchi
Abstract: A multi-deck circuit arrangement including a first deck circuit having a negative supply terminal and a second deck having a positive supply terminal connected to the negative supply terminal. A single power supply provides a voltage across both the first and second decks. The total power consumption will be less than the prior art of having both deck circuits conventionally regulated. The supply rail connecting the second deck's positive supply terminal to the first deck's negative supply terminal may be regulated. In one embodiment, the rail voltage can be controlled to optimize deck circuit operation for speed and power and to avoid level shifters when interfacing to other circuits.
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公开(公告)号：US09525362B2
公开(公告)日：2016-12-20
申请号：US13766496
申请日：2013-02-13
Applicant: GE Energy Power Conversion Technology Ltd.
Inventor： Pascal Monjean , Jerome Auguste
IPC: H02M3/335 , H02M3/337 , H02M5/458 , H02M7/08 , G05F1/585 , H02M7/42 , H02M1/10 , H02J3/38 , H02J11/00
Abstract: A power supply system for a charge is provided. The power supply system includes a converter connected in input to a current source and in output to a charge, the converter being able to deliver a direct current to the charge and allow the circulation of the current in a single direction, from the current source to the charge and a circulation bus for an electric current, including a first end and a second end. The power supply system further includes a device for injecting an additional alternating voltage and at the second end of the circulation bus, the injection device being connected to the second end and a device for recovering the additional injected alternating voltage, the recovery device being connected between the first end of the bus and the charge, so as to supply the charge with electrical current.
Abstract translation: 提供充电电源系统。 电源系统包括转换器，其连接到电流源的输入端并输出到电荷，转换器能够将直流电流传送到电荷并允许电流沿着从电流源到单个方向的循环 电荷和用于电流的循环总线，包括第一端和第二端。 电源系统还包括用于注入附加交流电压的装置，并且在循环总线的第二端处，注入装置连接到第二端，以及用于恢复附加注入的交流电压的装置，所述恢复装置连接在 总线的第一端和充电，以便为电流供电。
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公开(公告)号：US08461814B2
公开(公告)日：2013-06-11
申请号：US12840674
申请日：2010-07-21
Applicant: Benoît Peron
Inventor： Benoît Peron
CPC classification number: H02M3/158
Abstract: A power supply circuit capable of providing two regulated voltages based on a D.C. input voltage, including a boost converter and a buck-boost converter, the circuit including a single inductive element common to the boost and buck-boost converters.
Abstract translation: 一种能够基于直流输入电压（包括升压转换器和降压 - 升压转换器）提供两个调节电压的电源电路，该电路包括升压和降压 - 升压转换器共用的单个电感元件。
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10.发明授权Circuit and method for generating body bias voltage for an integrated circuit 有权用于产生集成电路体偏置电压的电路和方法公开(公告)号：US08416011B2
公开(公告)日：2013-04-09
申请号：US12941104
申请日：2010-11-08
Applicant: Srinivas Reddy Chokka , Prasad Sawarkar
Inventor： Srinivas Reddy Chokka , Prasad Sawarkar
CPC classification number: G06F1/26
Abstract: A circuit includes a PMOS body bias circuit including a PMOS charge pump for generating a positive supply voltage, a PMOS reference voltage generator for providing a PMOS reference voltage, and a PMOS linear voltage regulator circuit for generating a PMOS body bias voltage upon receiving the positive supply voltage and the PMOS reference voltage. The circuit also includes a NMOS body bias circuit including a NMOS charge pump for generating a negative supply voltage, a NMOS reference voltage generator for providing a NMOS reference voltage, and a NMOS linear voltage regulator circuit for generating a NMOS body bias voltage upon receiving the negative supply voltage and the NMOS reference voltage. The PMOS body bias voltage and the NMOS body bias voltage drive bulk of PMOS and NMOS devices in the integrated circuit.
Abstract translation: 电路包括PMOS体偏置电路，PMOS体偏置电路包括用于产生正电源电压的PMOS电荷泵，用于提供PMOS参考电压的PMOS参考电压发生器和用于在接收到正极时产生PMOS体偏置电压的PMOS线性电压调节器电路 电源电压和PMOS参考电压。 电路还包括NMOS体偏置电路，其包括用于产生负电源电压的NMOS电荷泵，用于提供NMOS参考电压的NMOS参考电压发生器和用于在接收到NMOS电压时产生NMOS体偏置电压的NMOS线性电压调节器电路 负电源电压和NMOS参考电压。 PMOS体偏置电压和NMOS体偏置电压驱动集成电路中PMOS和NMOS器件的体积。
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