Computer network packet transmission timing

    公开(公告)号:US12052332B2

    公开(公告)日:2024-07-30

    申请号:US17162098

    申请日:2021-01-29

    CPC classification number: H04L69/28 H03M13/09 H04J3/0644 H04J3/065 H04L49/9078

    Abstract: Establishing an expected transmit time at which a network interface controller (NIC) is expected to transmit a next packet. Enqueuing, with the NIC and before the expected transmit time, a packet P1 to be transmitted at the expected transmit time. Upon enqueuing P1, incrementing the expected transmit time by an expected transmit duration of P1. Transmitting at the NIC's line rate and timestamping enqueued P1 with its actual transmit time. Adjusting the expected transmit time by a difference between P1's actual transmit and P1's expected transmit time. Requesting, before completion of transmitting P1, to transmit a P2 at time t(P2). Enqueuing, in sequence, zero or more P0, such that the current expected transmit time plus the duration of the transmission of the P0s at the line rate equals t(P2). Transmitting at the line rate each enqueued P0. Upon enqueuing each P0, incrementing, for each P0, the expected transmit time by the expected transmit duration of the P0. Enqueuing P2 for transmission directly following enqueuing the final P0. Transmitting, by the NIC, enqueued P2 at t(P2).

    SYNCHRONIZATION METHOD AND APPARATUS, DEVICE, AND STORAGE MEDIUM

    公开(公告)号:US20240154713A1

    公开(公告)日:2024-05-09

    申请号:US17769525

    申请日:2020-10-09

    CPC classification number: H04J3/065 H04J3/1652

    Abstract: The present application provides a synchronization method, a synchronization apparatus, a device, and a storage medium. The synchronization method includes: determining an interface event timestamp point of synchronization event information, and encapsulating the synchronization event information; and inserting the encapsulated synchronization event information into a synchronization information channel of a first preset frame or a second preset frame for performing transmission.

    Fault tolerant design for clock-synchronization systems

    公开(公告)号:US11799577B2

    公开(公告)日:2023-10-24

    申请号:US17891215

    申请日:2022-08-19

    Applicant: Google LLC

    CPC classification number: H04J3/0641 H04J3/065 H04L7/0016 H04L12/44

    Abstract: A system is provided for synchronizing clocks. The system includes a plurality of devices in a network, each device having a local clock. The system is configured to synchronize the local clocks according to a primary spanning tree, where the primary spanning tree has a plurality of nodes connected through a plurality of primary links, each node of the plurality of nodes representing a respective device of the plurality of devices. The system is also configured to compute a backup spanning tree before a failure is detected in the primary spanning tree, wherein the backup spanning tree includes one or more backup links that are different from the primary links. As such, upon detection of a failure in the primary spanning tree, the system reconfigures the plurality of devices such that clock synchronization is performed according to the backup spanning tree.

    FSYNC MISMATCH TRACKING
    4.
    发明公开

    公开(公告)号:US20230188237A1

    公开(公告)日:2023-06-15

    申请号:US17986704

    申请日:2022-11-14

    Inventor: Vivek Sarda

    CPC classification number: H04J3/065 H04J3/0617 H04J3/0605

    Abstract: A baseline difference is determined between a slave line card time stamp corresponding to a slave line card frame sync signal and a master line card time stamp corresponding to a master line card frame sync signal. The slave line card generates subsequent slave line card time stamps for subsequent slave line card frame sync signals and the master line card generates subsequent master line card time stamps for subsequent master line card frame sync signals. Current differences are determined between subsequent slave line card time stamps and the subsequent master line card time stamps and the current differences are compared to the baseline difference. When a mismatch difference occurs (current difference differs from the baseline difference), the mismatch difference causes a phase-locked loop in the master line card to be adjusted or an offset to be provided to the master line card time of day counter.

    System and method to achieve datapath latency symmetry through an OTN wrapper
    10.
    发明授权
    System and method to achieve datapath latency symmetry through an OTN wrapper 有权
    通过OTN包装器实现数据路径延迟对称的系统和方法

    公开(公告)号:US09473261B1

    公开(公告)日:2016-10-18

    申请号:US14284110

    申请日:2014-05-21

    Abstract: A method of enabling transport of symmetric latency-sensitive constant-bit-rate (CBR) client data streams over an optical transport network (OTN) is provided. The method performs, utilizing an OTN wrapping device, an OTN wrapping operation on a received first constant-bit-rate (CBR) client data stream to form a first framed OTN data stream. The method determines a static wrapping delay induced on the first CBR client data stream by the OTN wrapping operation, performs, utilizing the OTN wrapping device, an OTN unwrapping operation on a received second framed OTN data stream to extract a second CBR client data stream from the second framed OTN data stream, determines a static unwrapping delay induced on the second framed OTN data stream by the OTN unwrapping operation, and equalizes the static wrapping and unwrapping delays by adjusting, at the OTN wrapping device, at least one of the static wrapping and unwrapping delays.

    Abstract translation: 提供了一种通过光传输网络(OTN)传输对称等待时间敏感常数比特率(CBR)客户端数据流的方法。 该方法利用OTN包装装置对所接收的第一恒定比特率(CBR)客户端数据流进行OTN包装操作,以形成第一帧OTN数据流。 该方法通过OTN包装操作确定在第一CBR客户端数据流上引起的静态环绕延迟,利用OTN包装装置执行OTN解包操作,对接收到的第二帧OTN数据流进行OTN解包操作,从第 第二成帧OTN数据流通过OTN解包操作确定在第二成帧OTN数据流上引起的静态解包延迟,并且通过在OTN包装装置处调整至少一个静态包装来均衡静态包装和展开延迟 并解开延迟。

Patent Agency Ranking