公开(公告)号：US20170346392A1

公开(公告)日：2017-11-30

申请号：US15166250

申请日：2016-05-26

Applicant: HIMAX TECHNOLOGIES LIMITED

Inventor： Cheng-Chin LIU ,  Min-Hsueh HSIEH ,  Yung-Jie LUO

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M3/073 ,  H02M2003/076

Abstract: The charge pump circuit includes multiple boosting stages, and each stage includes following units. A first switch circuit is controlled by a first clock signal to couple a second terminal of a first capacitor to a first input terminal or a second input terminal. A third switch circuit is controlled by a second clock signal to couple a second terminal of a second capacitor to the first input terminal or the second input terminal. A second switch circuit is controlled by electric potentials on the second capacitor to couple a first terminal of the first capacitor to the first input terminal or an output terminal. The fourth switch circuit is controlled by electric potentials on the first capacitor to couple a first terminal of the second capacitor to the first input terminal or the output terminal.

公开(公告)号：US09484810B2

公开(公告)日：2016-11-01

申请号：US14176441

申请日：2014-02-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takayuki Teraguchi

IPC: H02M3/07 ,  H03K3/03

CPC classification number: H02M3/073 ,  H02M2003/071 ,  H02M2003/072 ,  H02M2003/076 ,  H03K3/0315

Abstract: A regulator includes a capacitor connected between a ground terminal and an output terminal at which a first voltage is supplied. The first voltage is higher than a power source voltage supplied to the regulator. A feedback circuit in the regulator is configured to output a boost signal corresponding to a comparison between the first voltage and a threshold voltage value. A clock generating circuit includes an oscillator circuit that outputs an oscillation signal and a buffer circuit that outputs a clock signal according to the oscillation signal. The clock signal has an electric current level that is controlled in accordance with the boost signal. A charge pump outputs the first voltage in accordance with the clock signal.

Abstract translation: 调节器包括连接在接地端子和提供第一电压的输出端子之间的电容器。 第一电压高于提供给调节器的电源电压。 调节器中的反馈电路被配置为输出对应于第一电压和阈值电压值之间的比较的升压信号。 时钟发生电路包括输出振荡信号的振荡电路和根据振荡信号输出时钟信号的缓冲电路。 时钟信号具有根据升压信号来控制的电流电平。 电荷泵根据时钟信号输出第一电压。

公开(公告)号：US20150048809A1

公开(公告)日：2015-02-19

申请号：US14176441

申请日：2014-02-10

Applicant: KABUSHIKI KAISHA TOSHIBA

Inventor： Takayuki TERAGUCHI

IPC: H02M3/07

CPC classification number: H02M3/073 ,  H02M2003/071 ,  H02M2003/072 ,  H02M2003/076 ,  H03K3/0315

Abstract: A regulator includes a capacitor connected between a ground terminal and an output terminal at which a first voltage is supplied. The first voltage is higher than a power source voltage supplied to the regulator. A feedback circuit in the regulator is configured to output a boost signal corresponding to a comparison between the first voltage and a threshold voltage value. A clock generating circuit includes an oscillator circuit that outputs an oscillation signal and a buffer circuit that outputs a clock signal according to the oscillation signal. The clock signal has an electric current level that is controlled in accordance with the boost signal. A charge pump outputs the first voltage in accordance with the clock signal.

Abstract translation: 调节器包括连接在接地端子和提供第一电压的输出端子之间的电容器。 第一电压高于提供给调节器的电源电压。 调节器中的反馈电路被配置为输出对应于第一电压和阈值电压值之间的比较的升压信号。 时钟发生电路包括输出振荡信号的振荡电路和根据振荡信号输出时钟信号的缓冲电路。 时钟信号具有根据升压信号来控制的电流电平。 电荷泵根据时钟信号输出第一电压。

公开(公告)号：US20140375378A1

公开(公告)日：2014-12-25

申请号：US13924875

申请日：2013-06-24

Applicant: SanDisk Technologies Inc.

Inventor： Behdad Youssefi

IPC: H02M3/18

CPC classification number: H02M3/18 ,  H02M3/073 ,  H02M2003/076

Abstract: A charge pump system uses a helper pump to use in generating a boosted clock signal to use for the stages capacitor of a charge pump and also for the gate clock of the stage. This can be particularly useful in applications with lower supply levels, where a the helper pump can be used to provide an amplitude higher than the supply level, that can then be added to the supply level for the boosted clock signal and then added again to the supply level for the gate clock. Further advantages can be obtained by using the helper or auxiliary pump as an input to an optimized inverter circuit that receives an input clock and has an output that initially rises to the supply level than subsequently to the auxiliary pump's level.

Abstract translation: 电荷泵系统使用辅助泵来产生用于电荷泵的级电容器以及级的栅极时钟的升压时钟信号。 这可以在具有较低电源电平的应用中特别有用，其中辅助泵可用于提供高于电源电平的幅度，然后可以将其加到升压时钟信号的电源电平，然后再次添加到 门时钟的供电电平。 通过使用辅助泵或辅助泵作为接收输入时钟的优化逆变器电路的输入并且具有最初上升到供应水平的输出，而不是辅助泵的水平以后，可以获得进一步的优点。

公开(公告)号：US08742836B2

公开(公告)日：2014-06-03

申请号：US13556182

申请日：2012-07-23

Applicant: Yen-An Chang ,  Hao-Jan Yang

Inventor： Yen-An Chang ,  Hao-Jan Yang

IPC: G05F1/10

CPC classification number: H02M3/073 ,  H02M2003/076 ,  H03K5/003

Abstract: A double-swing clock generator includes a first double-swing clock generation circuit and a second double-swing clock generation circuit. The first double-swing clock generation circuit is used for receiving a first voltage, a second voltage, a first clock, an inverse first clock, and a third voltage, and outputting a first double-swing clock. The second double-swing clock generation circuit is used for receiving a fourth voltage, the second voltage, the first clock, the inverse first clock, and the third voltage, and outputting a second double-swing clock.

Abstract translation: 双摆时钟发生器包括第一双摆时钟发生电路和第二双摆时钟产生电路。 第一双摆时钟产生电路用于接收第一电压，第二电压，第一时钟，反相第一时钟和第三电压，并输出第一双摆时钟。 第二双摆时钟产生电路用于接收第四电压，第二电压，第一时钟，反相第一时钟和第三电压，并输出第二双摆时钟。

公开(公告)号：US20120313679A1

公开(公告)日：2012-12-13

申请号：US13341004

申请日：2011-12-30

Applicant: Chae Kyu JANG

Inventor： Chae Kyu JANG

IPC: H03L7/093

CPC classification number: H02M3/073 ,  H02M2003/076

Abstract: A pump circuit includes a first clock generation unit, a second clock generation unit and a pumping stage unit. The first clock generation unit is configured to generate a first clock with a first amplitude by using an input clock and an external voltage. The second clock generation unit is configured to generate a second clock with a second amplitude larger than the first amplitude by using the input clock and an amplified voltage generated by amplifying the external voltage. The pumping stage unit is configured to increase an input voltage using the first clock and the second clock and generate amplified output voltages.

Abstract translation: 泵电路包括第一时钟生成单元，第二时钟生成单元和泵送单元。 第一时钟生成单元被配置为通过使用输入时钟和外部电压来产生具有第一幅度的第一时钟。 第二时钟生成单元被配置为通过使用输入时钟和通过放大外部电压产生的放大电压来产生具有大于第一幅度的第二幅度的第二时钟。 泵送级单元被配置为使用第一时钟和第二时钟增加输入电压并产生放大的输出电压。

公开(公告)号：US20120139619A1

公开(公告)日：2012-06-07

申请号：US13171135

申请日：2011-06-28

Applicant: Pil Seon YOO

Inventor： Pil Seon YOO

IPC: G05F3/24

CPC classification number: H02M3/073 ,  H02M2003/076

Abstract: A high voltage generator includes a negative bias generator configured to generate a negative bias, a clock generator configured to generate a clock signal that toggles between a positive bias and the negative bias, a clock doubling circuit configured to raise the positive bias of the clock signal and to output the clock signal having the raised positive bias as a second clock signal, and a charge pump configured to generate a high voltage using the second clock signal having the raised positive bias.

Abstract translation: 高电压发生器包括被配置为产生负偏压的负偏压发生器，被配置为产生在正偏压和负偏压之间切换的时钟信号的时钟发生器，被配置为升高时钟信号的正偏置的时钟倍增电路 并输出具有升高的正偏压的时钟信号作为第二时钟信号;以及电荷泵，配置为使用具有升高的正偏压的第二时钟信号产生高电压。

公开(公告)号：US20100109628A1

公开(公告)日：2010-05-06

申请号：US12655742

申请日：2010-01-05

Applicant: Jong Ho Jung

Inventor： Jong Ho Jung

IPC: G05F1/10

CPC classification number: H02M3/07 ,  H02M2003/076

Abstract: A clock control circuit is provided. The clock control circuit includes a voltage supplier for supplying a first voltage in response to a first clock signal, a voltage booster for boosting the first voltage in response to the first clock signal input to the voltage booster, and a clock generator for generating a second clock signal having a voltage level equal to the boosted first voltage in response to the first clock signal.

公开(公告)号：US20070057898A1

公开(公告)日：2007-03-15

申请号：US10557799

申请日：2004-05-14

Applicant: Yoshiharu Nakajima ,  Yoshitoshi Kida

Inventor： Yoshiharu Nakajima ,  Yoshitoshi Kida

IPC: G09G3/36

CPC classification number: H02M3/073 ,  H02M2003/076

Abstract: A supply voltage conversion circuit allowing fabrication of a charge pump circuit having a large current capability with a small area is provided. In a charge pump DC-DC converter (10) for converting a supply voltage VDD1 to a supply voltage VDD2, a level shifter (12) implements amplitude conversion to convert from a control pulse with amplitude of VSS-VDD1 to a control pulse with amplitude of VSS-VDD2. By using the control pulse having the converted amplitude as a pumping pulse, a flying capacitor (C11) is charged/discharged by MOS transistors (Qp11), and (Qn11) of a charge pump circuit (11), and switching of MOS transistors (Qn12), and (Qp12) coupled to the output of the flying capacitor (C11) is controlled.

Abstract translation: 提供了允许制造具有小面积的具有大电流能力的电荷泵电路的电源电压转换电路。 在用于将电源电压VDD 1转换为电源电压VDD 2的电荷泵DC-DC转换器（10）中，电平转换器（12）进行幅度转换，以将具有VSS-VDD1幅度的控制脉冲转换为控制 具有VSS-VDD幅度的脉冲。通过使用具有转换幅度的控制脉冲作为泵浦脉冲，通过MOS晶体管（Qp 11）和（Qn 11）对充电电容（C 11）进行充电/放电 泵电路（11）和耦合到飞跨电容器（C 11）的输出的MOS晶体管（Qn 12）和（Qp 12）的切换被控制。

公开(公告)号：US07005912B2

公开(公告)日：2006-02-28

申请号：US10684441

申请日：2003-10-15

Applicant: Yoshihiro Nonaka

Inventor： Yoshihiro Nonaka

IPC: G05F1/10 ,  G05F3/02

CPC classification number: H02M3/073 ,  H02M2001/009 ,  H02M2003/071 ,  H02M2003/076

Abstract: In a step-up apparatus, a first level shift circuit receives a first clock signal to generate two phase-opposite second clock signals, and a second level shift circuit receives the first clock signal to generate two phase-opposite third clock signals. A charge pump circuit steps up a power supply voltage at a power supply voltage terminal using the second clock signals to generate a positive voltage, and a polarity inverting circuit inverts the positive voltage using the third clock signals to generate a negative voltage whose absolute value is the same as the positive voltage. A high level of the second clock signals is not higher than the positive voltage, and a low level of the second clock signals is not lower than a voltage at a ground terminal. A high level of the third clock signals is not higher than the power supply voltage, and a low level of the third clock signals is not lower than the negative voltage.

Abstract translation: 在升压装置中，第一电平移位电路接收第一时钟信号以产生两个相对第二时钟信号，第二电平移位电路接收第一时钟信号以产生两个相反的第三时钟信号。 电荷泵电路使用第二时钟信号来升高电源电压端子处的电源电压，以产生正电压，并且极性反转电路使用第三时钟信号来反转正电压，以产生绝对值为 与正电压相同。 高电平的第二时钟信号不高于正电压，第二时钟信号的低电平不低于接地端子处的电压。 高电平的第三时钟信号不高于电源电压，并且第三时钟信号的低电平不低于负电压。