CONTROL OF HYSTERETIC CURRENT MODE MULTILEVEL BUCK CONVERTER

    公开(公告)号:US20240258920A1

    公开(公告)日:2024-08-01

    申请号:US18500360

    申请日:2023-11-02

    CPC classification number: H02M3/158 H02M1/0003 H02M1/0095 H02M3/07 H02M7/4837

    Abstract: A method of controlling a multilevel power converter may include measuring an input voltage at a converter input, determining a half input voltage based on the input voltage; measuring a flying capacitor voltage across the flying capacitor; determining an error voltage based on a difference between the flying capacitor voltage and the half input voltage; generating an inductor current window having an inductor peak current and a valley inductor current; modulating the inductor peak current into an upper inductor peak current and a lower inductor peak current based on the error voltage; and operating the multilevel power converter to produce an output current through an inductor to a converter output, the output current being within the inductor current window and based on a sequence of pulse width modulation states.

    Battery path impedance compensation

    公开(公告)号:US12027979B2

    公开(公告)日:2024-07-02

    申请号:US17198899

    申请日:2021-03-11

    Applicant: Apple Inc.

    CPC classification number: H02M3/1582 H02J7/02 H02M1/0003 H02J2207/20

    Abstract: A power system for a battery powered device can include a first stage power converter, a charge injector, and a bypass switch. The first stage power converter can be configured to have an input coupled to a battery and operable to convert a battery voltage to a level higher than a main voltage bus of the battery powered device. The charge injector can include an input coupled to the output of the power converter and an output configured to be coupled to the main voltage bus. The bypass can include one or more bypass switches operable to selectively couple an output of the power converter to the main voltage bus, bypassing the charge injector. The charge injector may be selectively operable as a current source configured to draw power from an output of the power converter and the battery to reduce voltage dips of the main voltage bus.

    Power conversion device
    9.
    发明授权

    公开(公告)号:US11973437B2

    公开(公告)日:2024-04-30

    申请号:US17792712

    申请日:2020-03-30

    Abstract: A power conversion device includes, for respective phases of an AC circuit, leg circuits each having a pair of arms connected in series to each other, each arm including a plurality of converter cells which are connected in series and each of which has an energy storage element. A controlling circuitry includes a zero-phase-sequence voltage command value adjustment unit for correcting arm voltage command values for the arms by a zero-phase-sequence voltage command value. The command value correction circuitry performs adjustment control for adjusting the zero-phase-sequence voltage command value so that at least one arm voltage command value becomes equivalent to a limit value of the output voltage range of the arm.

    High performance feedback loop with delay compensation

    公开(公告)号:US11967963B2

    公开(公告)日:2024-04-23

    申请号:US17690063

    申请日:2022-03-09

    Inventor: Raanan Ivry

    CPC classification number: H03L7/0994 H02M1/0003 H03M3/37

    Abstract: An Integrated Circuit (IC) includes feedback control-loop (FCL) circuitry to generate a delay-compensated output signal responsively to an input reference signal. The FCL circuitry includes a main feedback path, a first subtractor, a delay-compensation feedback path, and a second subtractor. The main feedback path is to generate a main feedback signal responsively to the delay-compensated output signal. The first subtractor is to generate a non-compensated output signal responsively to a difference between the main feedback signal and the input reference signal. The delay-compensation feedback path is to generate a delay-compensation feedback signal responsively to the delay-compensated output signal. The second subtractor is to generate the delay-compensated output signal responsively to a difference between the non-compensated output signal and the delay-compensation feedback signal.

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