公开(公告)号：US11860804B2

公开(公告)日：2024-01-02

申请号：US17364924

申请日：2021-07-01

Applicant: REALTEK SEMICONDUCTOR CORPORATION

Inventor： Chen-Tung Lin ,  Yue-Feng Chen

IPC: G06F13/30

CPC classification number: G06F13/30 ,  G06F2211/002 ,  G06F2213/28

Abstract: A direct memory access (DMA) controller, an electronic device that uses the DMA controller, and a method of operating the DMA controller are provided. The DMA controller is configured to access a memory that contains a privilege area and a normal area. The method of operating the DMA controller includes the following steps: searching for a DMA channel that is in an idle state in the DMA controller; setting a register value of a mode register of the DMA channel such that the DMA channel operates in a privilege mode; setting a memory address register and a byte count register of the DMA channel; and controlling the DMA channel to transfer data based on the memory address register and the byte count register.

公开(公告)号：US20180349310A1

公开(公告)日：2018-12-06

申请号：US15610611

申请日：2017-05-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Srivani Kor KORIGINJA RAMASWAMY ,  Yiling ZHANG ,  Stewart Hoang NGUYEN

IPC: G06F13/40 ,  G06F11/27 ,  G06F13/10

CPC classification number: G06F13/4081 ,  G06F11/27 ,  G06F13/10 ,  G06F2211/002 ,  G06F2213/0026 ,  G06F2213/4004

Abstract: Examples provided herein relate to hot plugging PCIe cards. For example, a field programmable gate array (“FPGA”) communicably coupled to a PCIe bus may detect a new PCIe card physically connected to the PCIe bus. The FPGA may access configuration information stored by the FPGA that is associated with the PCIe bus. The FPGA may determine, based on the accessed configuration information, whether to facilitate connection of the new PCIe card to the PCIe bus. Responsive to determining that connection of the new PCIe card to the PCIe bus should be facilitated, the new PCIe card may be trained to communicate with the PCIe bus and an upstream device communicably coupled to the PCIe bus.

公开(公告)号：US09824027B2

公开(公告)日：2017-11-21

申请号：US13939927

申请日：2013-07-11

Applicant: Intelligent Intellectual Property Holdings 2, LLC

Inventor： David Flynn ,  David Atkisson ,  Bert Lagerstedt ,  John Strasser ,  Jonathan Thatcher ,  Michael Zappe

IPC: G06F12/02 ,  G06F12/121 ,  G06F1/18 ,  G06F3/06 ,  G06F9/52 ,  G06F11/10 ,  G06F12/0804 ,  G06F12/0868 ,  G06F13/28 ,  G06F13/40 ,  H05K7/14 ,  G06F13/42 ,  G06F12/12 ,  G06F12/123 ,  H04L29/08

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/02 ,  H04L67/1097 ,  H05K7/1444 ,  H05K7/1487 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus and system are disclosed for a storage area network (“SAN”). In one embodiment, a computer system includes an internal storage device and an internal storage controller. In this embodiment, the internal storage controller is configured to implement a SAN that includes at least the internal storage device and a storage device external to the computer system. In this embodiment, the internal storage controller is further configured to service a storage request received from a client that involves data stored by the internal storage device. In this embodiment, the internal storage controller is configured to communicate with the external storage device via a network.

公开(公告)号：US20170185347A1

公开(公告)日：2017-06-29

申请号：US15460126

申请日：2017-03-15

Applicant: Longitude Enterprise Flash S.A.R.L.

Inventor： David Flynn ,  Jonathan Thatcher ,  Michael Zappe

IPC: G06F3/06 ,  G06F9/54 ,  G06F12/02

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/02 ,  H04L67/1097 ,  H05K7/1444 ,  H05K7/1487 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus, system, and method are disclosed for managing a non-volatile storage medium. A storage controller receives a message that identifies data that no longer needs to be retained on the non-volatile storage medium. The data may be identified using a logical identifier. The message may comprise a hint, directive, or other indication that the data has been erased and/or deleted. In response to the message, the storage controller records an indication that the contents of a physical storage location and/or physical address associated with the logical identifier do not need to be preserved on the non-volatile storage medium.

公开(公告)号：US09519594B2

公开(公告)日：2016-12-13

申请号：US13648009

申请日：2012-10-09

Applicant: Fusion-io, Inc.

Inventor： David Flynn ,  John Strasser ,  Jonathan Thatcher ,  Michael Zappe

IPC: G06F12/12 ,  G06F13/42 ,  H04L29/08 ,  G06F9/52 ,  G06F12/08 ,  G06F13/40 ,  H05K7/14 ,  G06F12/02 ,  G06F1/18 ,  G06F3/06 ,  G06F11/10 ,  G06F13/28

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/02 ,  H04L67/1097 ,  H05K7/1444 ,  H05K7/1487 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus, system, and method are disclosed for solid-state storage as cache for high-capacity, non-volatile storage. The apparatus, system, and method are provided with a plurality of modules including a cache front-end module and a cache back-end module. The cache front-end module manages data transfers associated with a storage request. The data transfers between a requesting device and solid-state storage function as cache for one or more HCNV storage devices, and the data transfers may include one or more of data, metadata, and metadata indexes. The solid-state storage may include an array of non-volatile, solid-state data storage elements. The cache back-end module manages data transfers between the solid-state storage and the one or more HCNV storage devices.

Abstract translation: 公开了一种用于固态存储作为高容量，非易失性存储的高速缓存的装置，系统和方法。 该装置，系统和方法具有包括高速缓存前端模块和高速缓存后端模块的多个模块。 缓存前端模块管理与存储请求相关联的数据传输。 在请求设备和固态存储功能之间的数据作为一个或多个HCNV存储设备的高速缓存传输，并且数据传输可以包括数据，元数据和元数据索引中的一个或多个。 固态存储器可以包括非易失性固态数据存储元件阵列。 高速缓存后端模块管理固态存储与一个或多个HCNV存储设备之间的数据传输。

公开(公告)号：US09495317B2

公开(公告)日：2016-11-15

申请号：US14132831

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  David Astrom

IPC: G06F13/00 ,  G06F13/40

CPC classification number: G06F13/4022 ,  G06F2211/002

Abstract: A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Abstract translation: 总线驱动器电路可以包括第一和第二电路节点，其中第一电路节点可操作地耦合到总线线路，这导致第一和第二电路节点之间的总线电容。 开关电路耦合到第一电路节点并被配置为在第一和第二电路节点之间施加输出电压。 从而当控制信号表示主导状态时，总线电容被充电。 放电电路包括至少一个电阻器。 放电电路耦合在第一和第二电路节点之间，并且被配置为当控制信号指示隐性状态时允许总线电容经由电阻放电。 开关电路还被配置为提供用于在从显性状态到隐性状态的过渡期期间对总线电容放电的临时电流通路。

公开(公告)号：US09454492B2

公开(公告)日：2016-09-27

申请号：US13730602

申请日：2012-12-28

Applicant: Intelligent Intellectual Property Holdings 2, LLC

Inventor： David Flynn ,  Bert Lagerstedt ,  John Strasser ,  Jonathan Thatcher ,  John Walker ,  Michael Zappe

IPC: G06F3/00 ,  G06F13/00 ,  G06F12/12 ,  G06F1/18 ,  G06F3/06 ,  G06F9/52 ,  G06F11/10 ,  G06F12/02 ,  G06F12/08 ,  G06F13/28 ,  G06F13/40 ,  H05K7/14 ,  G06F13/42 ,  H04L29/08

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/02 ,  H04L67/1097 ,  H05K7/1444 ,  H05K7/1487 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: One method includes streaming a data segment to a write buffer corresponding to a virtual page including at least two physical pages. Each physical page is defined within a respective solid-state storage element. The method also includes programming contents of the write buffer to the virtual page, such that a first portion of the data segment is programmed to a first one of the physical pages, and a second portion of the data segment is programmed to a second one of the physical pages.

Abstract translation: 一种方法包括将数据段流式传输到与包括至少两个物理页面的虚拟页面相对应的写入缓冲器。 每个物理页面在相应的固态存储元件内定义。 该方法还包括将写入缓冲器的内容编程到虚拟页面，使得数据段的第一部分被编程到物理页面中的第一个，并且数据段的第二部分被编程为第二个 物理页面。

公开(公告)号：US20150205661A1

公开(公告)日：2015-07-23

申请号：US14158935

申请日：2014-01-20

Applicant: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.

Inventor： Jonathan L. KAUS ,  Adam C. LANGE-PEARSON ,  Gary R. RICARD ,  Jaimeson SALEY

IPC: G06F11/07 ,  G06F13/24

CPC classification number: G06F11/0745 ,  G06F9/327 ,  G06F9/38 ,  G06F11/0706 ,  G06F11/0721 ,  G06F11/0772 ,  G06F11/0784 ,  G06F11/0793 ,  G06F13/24 ,  G06F2201/81 ,  G06F2211/002

Abstract: A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.

Abstract translation: 一种用于处理分级寄存器结构中的中断的方法，处理器和计算机系统。 该方法包括使用系统中断处理程序在根级别寄存器处接收在寄存器结构中的较低级别寄存器处发生的中断的指示，以调用分配给包括较低级别的结构的一组寄存器的错误处理器 注册和使用调用的错误处理程序来处理中断并返回到系统中断处理程序。

公开(公告)号：US20150169488A1

公开(公告)日：2015-06-18

申请号：US14132831

申请日：2013-12-18

Applicant: Infineon Technologies AG

Inventor： Dieter Metzner ,  Peter Widerin ,  David Astrom

IPC: G06F13/40

CPC classification number: G06F13/4022 ,  G06F2211/002

Abstract: A bus driver circuit may include a first and a second circuit node, wherein the first circuit node is operably coupled to a bus line, which causes a bus capacitance between the first and the second circuit node. A switching circuit is coupled to the first circuit node and configured to apply an output voltage between the first and the second circuit node. Thereby the bus capacitance is charged when a control signal indicates a dominant state. A discharge circuit comprises at least one resistor. The discharge circuit is coupled between the first and the second circuit node and configured to allow the bus capacitance to discharge via the resistor when the control signal indicates a recessive state. The switching circuit is further configured to provide a temporary current path for discharging the bus capacitance during a transition period from a dominant to a recessive state.

Abstract translation: 总线驱动器电路可以包括第一和第二电路节点，其中第一电路节点可操作地耦合到总线线路，这导致第一和第二电路节点之间的总线电容。 开关电路耦合到第一电路节点并被配置为在第一和第二电路节点之间施加输出电压。 从而当控制信号表示主导状态时，总线电容被充电。 放电电路包括至少一个电阻器。 放电电路耦合在第一和第二电路节点之间，并且被配置为当控制信号指示隐性状态时允许总线电容经由电阻放电。 开关电路还被配置为提供用于在从显性状态到隐性状态的过渡期期间对总线电容放电的临时电流通路。

公开(公告)号：US20120324311A1

公开(公告)日：2012-12-20

申请号：US13600077

申请日：2012-08-30

Applicant: David Flynn ,  Bert Lagerstedt ,  John Strasser ,  Jonathan Thatcher ,  Michael Zappe

Inventor： David Flynn ,  Bert Lagerstedt ,  John Strasser ,  Jonathan Thatcher ,  Michael Zappe

IPC: H03M13/05 ,  G06F11/08 ,  G11C16/02

CPC classification number: G06F12/121 ,  G06F1/183 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0613 ,  G06F3/0619 ,  G06F3/0643 ,  G06F3/065 ,  G06F3/0652 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0685 ,  G06F3/0688 ,  G06F9/52 ,  G06F9/54 ,  G06F11/108 ,  G06F12/0246 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/12 ,  G06F12/123 ,  G06F13/28 ,  G06F13/4022 ,  G06F13/426 ,  G06F2211/002 ,  G06F2211/103 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/222 ,  G06F2212/69 ,  G06F2212/70 ,  G06F2212/7205 ,  H04L67/02 ,  H04L67/1097 ,  H05K7/1444 ,  H05K7/1487 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: An apparatus, system, and method are disclosed for managing data in a solid-state storage device. A solid-state storage and solid-state controller are included. The solid-state storage controller includes a write data pipeline and a read data pipeline The write data pipeline includes a packetizer and an ECC generator. The packetizer receives a data segment and creates one or more data packets sized for the solid-state storage. The ECC generator generates one or more error-correcting codes (“ECC”) for the data packets received from the packetizer. The read data pipeline includes an ECC correction module, a depacketizer, and an alignment module. The ECC correction module reads a data packet from solid-state storage, determines if a data error exists using corresponding ECC and corrects errors. The depacketizer checks and removes one or more packet headers. The alignment module removes unwanted data, and re-formats the data as data segments of an object.

Abstract translation: 公开了用于管理固态存储设备中的数据的装置，系统和方法。 包括固态存储和固态控制器。 固态存储控制器包括写数据流水线和读数据管线。写数据流水线包括打包器和ECC发生器。 打包器接收数据段并创建一个或多个数据包，以便固态存储。 ECC发生器为从分组器接收到的数据分组生成一个或多个纠错码（ECC）。 读取数据流水线包括ECC校正模块，解包器和对准模块。 ECC校正模块从固态存储读取数据包，使用对应的ECC确定是否存在数据错误，并纠正错误。 拆包器检查并删除一个或多个数据包头。 对齐模块删除不需要的数据，并将数据重新格式化为对象的数据段。