公开(公告)号：US08048614B2

公开(公告)日：2011-11-01

申请号：US11463467

申请日：2006-08-09

申请人： Yoshihiko Okamoto ,  Masami Ogita

发明人： Yoshihiko Okamoto ,  Masami Ogita

IPC分类号： H01L21/00

CPC分类号： G03F1/62 ,  G03F1/48 ,  G03F7/70308 ,  G03F7/706 ,  G03F7/70983 ,  Y10S438/975 ,  Y10S438/976

摘要： A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.

摘要翻译： 通过形成集成电路图案的掩模和缩小投影对准器，将具有比曝光光束的波长的一半更小的电路图案以优异的精度传输到半导体晶片平面上。 通过超分辨率曝光的协同效应提高了半导体晶片上的电路图形的转印精度，其中由集成电路掩模的图案侧设置由透明介质制成的掩模罩，以便抑制还原的像差 投影对准，以及在实施了平面化处理的半导体晶片的光致抗蚀剂侧上增加设置有由透明介质制成的晶片盖的光学还原投影透镜系统的实际孔径的数量的方法。

公开(公告)号：US20070117409A1

公开(公告)日：2007-05-24

申请号：US11463467

申请日：2006-08-09

申请人： Yoshihiko Okamoto ,  Masami Ogita

发明人： Yoshihiko Okamoto ,  Masami Ogita

IPC分类号： H01L21/31

CPC分类号： G03F1/62 ,  G03F1/48 ,  G03F7/70308 ,  G03F7/706 ,  G03F7/70983 ,  Y10S438/975 ,  Y10S438/976

摘要： A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.

摘要翻译： 通过形成集成电路图案的掩模和缩小投影对准器，将具有比曝光光束的波长的一半更小的电路图案以优异的精度传输到半导体晶片平面上。 通过超分辨率曝光的协同效应提高了半导体晶片上的电路图形的转印精度，其中由集成电路掩模的图案侧设置由透明介质制成的掩模罩，以便抑制还原的像差 投影对准，以及在实施了平面化处理的半导体晶片的光致抗蚀剂侧上增加设置有由透明介质制成的晶片盖的光学还原投影透镜系统的实际孔径的数量的方法。

公开(公告)号：US20110229824A1

公开(公告)日：2011-09-22

申请号：US12870752

申请日：2010-08-27

申请人： Yoshihiko OKAMOTO ,  Masami OGITA

发明人： Yoshihiko OKAMOTO ,  Masami OGITA

IPC分类号： G03F7/20

CPC分类号： G03F1/62 ,  G03F1/48 ,  G03F7/70308 ,  G03F7/706 ,  G03F7/70983 ,  Y10S438/975 ,  Y10S438/976

摘要： A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.

摘要翻译： 通过形成集成电路图案的掩模和缩小投影对准器，将具有比曝光光束的波长的一半更小的电路图案以优异的精度传输到半导体晶片平面上。 通过超分辨率曝光的协同效应提高了半导体晶片上的电路图形的转印精度，其中由集成电路掩模的图案侧设置由透明介质制成的掩模罩，以便抑制还原的像差 投影对准，以及在实施了平面化处理的半导体晶片的光致抗蚀剂侧上增加设置有由透明介质制成的晶片盖的光学还原投影透镜系统的实际孔径的数量的方法。