发明授权
- 专利标题: Semiconductor integrated circuit device fabrication method
- 专利标题(中): 半导体集成电路器件制造方法
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申请号: US11463467申请日: 2006-08-09
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公开(公告)号: US08048614B2公开(公告)日: 2011-11-01
- 发明人: Yoshihiko Okamoto , Masami Ogita
- 申请人: Yoshihiko Okamoto , Masami Ogita
- 申请人地址: JP Kikugawa-shi
- 专利权人: Yoshihiko Okamoto
- 当前专利权人: Yoshihiko Okamoto
- 当前专利权人地址: JP Kikugawa-shi
- 代理机构: Apex Juris, pllc
- 代理商 Tracy M. Heims
- 优先权: JPJP2004-031528 20040205
- 主分类号: H01L21/00
- IPC分类号: H01L21/00
摘要:
A circuit pattern having a size finer than a half of a wavelength of an exposure beam is transferred on a semiconductor wafer plane with an excellent accuracy by means of a mask whereupon an integrated circuit pattern is formed and a reduction projection aligner. The accuracy of transferring the circuit pattern on the semiconductor wafer is improved by synergic effects of super-resolution exposure, wherein a mask cover made of a transparent medium is provided on a pattern side of the integrated circuit mask so as to suppress the aberration of reduction projection alignment, and a method of increasing the number of actual apertures of the optical reduction projection lens system provided with the wafer cover made of the transparent medium on a photoresist side of the semiconductor wafer to which planarizing process is performed.
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