公开(公告)号：US5287063A

公开(公告)日：1994-02-15

申请号：US777638

申请日：1991-10-16

申请人： Masao Izawa

发明人： Masao Izawa

IPC分类号： G01R13/20 ,  G01R19/00 ,  G01R19/25 ,  G01R35/00

CPC分类号： G01R35/005

摘要： An automatic calibration circuit for a maximum and minimum value detection apparatus including a maximum value detection circuit for detecting and outputting a maximum value of an input signal, and a minimum value detection circuit for detecting and outputting a minimum value of the input signal. In a calibration mode, a reference signal of a fixed value is automatically inputted to the maximum value detection circuit and to the minimum value detection circuit upon entry of a calibration mode. An offset voltage of at least one of the maximum value detection circuit and the minimum value detection circuit is automatically adjusted so that the maximum value and the minimum value obtained in response to the reference signal become equal.

摘要翻译： 一种用于最大值和最小值检测装置的自动校准电路，包括用于检测和输出输入信号的最大值的最大值检测电路，以及用于检测和输出输入信号的最小值的最小值检测电路。 在校准模式中，在校准模式进入时，固定值的参考信号被自动输入到最大值检测电路和最小值检测电路。 自动调整最大值检测电路和最小值检测电路中的至少一个的偏移电压，使得响应于参考信号获得的最大值和最小值变得相等。

公开(公告)号：US5210538A

公开(公告)日：1993-05-11

申请号：US758617

申请日：1991-09-12

申请人： Masahiko Kuroiwa

发明人： Masahiko Kuroiwa

IPC分类号： G01R13/28 ,  H03M1/08 ,  H03M1/12

CPC分类号： H03M1/0863 ,  H03M1/12

摘要： A glitch detection circuit having an A/D converter, a state holding circuit, a discrimination circuit and a storing circuit. The A/D converter samples an input signal at a predetermined sampling interval to produce digital data during a predetermined acquisition interval which is longer or equal to the sampling interval. The state holding circuit is connected to an output terminal of the A/D converter, and holds a distribution state of the digital data in the predetermined acquisition interval. The discrimination circuit detects a maximum value and a minimum value during the acquisition interval based on the digital data held in the state holding circuit, and the storing circuit stores the maximum value and the minimum value produced from the discrimination circuit for each acquisition interval. The arrangement can obviate the need for the feedback loop that limits the operation speed in a conventional circuit, and can detect maximum values and the minimum values by using the state holding circuit and discriminating circuit arranged in cascade. The circuit can approximately double the operation speed of a conventional circuit, and hence can double the sampling frequency of the analog-to-digital converter. A glitch of a half pulse width can be detected.

摘要翻译： 具有A / D转换器，状态保持电路，鉴别电路和存储电路的毛刺检测电路。 A / D转换器以预定采样间隔对输入信号进行采样，以在长于或等于采样间隔的预定采集间隔期间产生数字数据。 状态保持电路连接到A / D转换器的输出端子，并且在预定的采集间隔中保持数字数据的分配状态。 识别电路基于保持在状态保持电路中的数字数据在采集间隔期间检测最大值和最小值，并且存储电路存储从每个采集间隔的鉴别电路产生的最大值和最小值。 该布置可以消除限制常规电路中的操作速度的反馈回路的需要，并且可以通过使用级联布置的状态保持电路和鉴别电路来检测最大值和最小值。 该电路可以使常规电路的操作速度大约翻倍，因此可以将模数转换器的采样频率提高一倍。 可以检测到半脉冲宽度的毛刺。

公开(公告)号：US5272449A

公开(公告)日：1993-12-21

申请号：US26081

申请日：1993-03-04

申请人： Masao Izawa

发明人： Masao Izawa

IPC分类号： G01R13/22 ,  G01R13/28 ,  G01R35/00 ,  H03F1/30 ,  H03G3/20 ,  H03F1/02

CPC分类号： G01R35/002 ,  G01R13/22 ,  G01R13/28 ,  H03F1/304

摘要： A vertical amplifier system for a multitrace oscilloscope including a first and a second variable gain amplifiers each connected to each channel of a multitrace oscilloscope. First, a first reference voltage is fed to the two variable gain amplifiers at the same time. The polarity of output of the second variable gain amplifier is inverted, and the inverted output is added to the output of the first variable gain amplifier by an adder. The added result is detected by a resistor. A CPU automatically controls a gain of at least one of the variable gain amplifiers while receiving the added result so that the added result becomes zero. Second, a second reference voltage (a ground level voltage, for example) is applied to both variable gain amplifiers, and an offset of at least one of the variable gain amplifiers is adjusted so that the added result detected by the resistor becomes zero. The input-output characteristics of both variable gain amplifiers are equalized with high accuracy.

摘要翻译： 一种用于多雷达示波器的垂直放大器系统，包括每个连接到多雷达示波器的每个通道的第一和第二可变增益放大器。 首先，将第一参考电压同时馈送到两个可变增益放大器。 第二可变增益放大器的输出极性反转，反相输出由加法器加到第一可变增益放大器的输出端。 附加结果由电阻检测。 CPU在接收到相加结果时自动控制至少一个可变增益放大器的增益，使得相加结果变为零。 第二，对两个可变增益放大器施加第二参考电压（例如地电平电压），并且调整至少一个可变增益放大器的偏移，使得由电阻器检测的相加结果变为零。 两个可变增益放大器的输入输出特性均具有高精度。

公开(公告)号：US5162750A

公开(公告)日：1992-11-10

申请号：US778377

申请日：1991-10-17

申请人： Takeshi Ito ,  Masao Izawa

发明人： Takeshi Ito ,  Masao Izawa

IPC分类号： H03H11/04 ,  H03F3/72 ,  H03H7/06 ,  H03H7/12

CPC分类号： H03F3/72

摘要： A band limiter connected between output lines of a differential amplifier. The band limiter includes a bipolar transistor connected to the output lines via capacitors, and includes a temperature detecting device for detecting ambient temperature. Transistor capacitance is connected to or disconnected from the output lines in response to a bandwidth limiting signal. The transistor constitutes a low-pass filter functioning as a band limiter when it is closed, whereas it functions as a variable capacitor which varies its capacitance in accordance with the ambient temperature when it is opened. The high-band frequency characteristic of the differential amplifier is temperature compensated by the transistor functioning as a variable capacitance.

摘要翻译： 连接在差分放大器的输出线之间的限幅器。 带限制器包括通过电容器连接到输出线的双极晶体管，并且包括用于检测环境温度的温度检测装置。 响应于带宽限制信号，晶体管电容与输出线连接或断开。 晶体管构成低通滤波器，当它被关闭时用作带限制器，而它用作可变电容器，其在打开时根据环境温度改变其电容。 差分放大器的高频带特性由作为可变电容的晶体管进行温度补偿。

公开(公告)号：US5155449A

公开(公告)日：1992-10-13

申请号：US755065

申请日：1991-09-05

申请人： Takeshi Ito

发明人： Takeshi Ito

IPC分类号： H03F1/42 ,  H03F1/56 ,  H03F3/34 ,  H03F3/50 ,  H03K5/02 ,  H03K19/017

CPC分类号： H03F3/505 ,  H03K19/01707 ,  H03K5/023 ,  H03F2203/5012 ,  H03F2203/5021 ,  H03F2203/5024 ,  H03F2203/5031

摘要： An FET buffer amplifier having a serially connected input FET and bias current FET. The drain or source current of the input FET is detected by a detection resistor and the detected voltage is negatively fed back to the gate of the bias current FET so that the source current of the input FET is maintained at a fixed value. This can achieve a low output impedance, high input impedance, wideband buffer amplifier with a simple circuit.

摘要翻译： 具有串联连接的输入FET和偏置电流FET的FET缓冲放大器。 输入FET的漏极或源极电流由检测电阻检测，检测到的电压反馈回偏置电流FET的栅极，使得输入FET的源极电流保持在固定值。 这可以实现低输出阻抗，高输入阻抗，宽带缓冲放大器具有简单的电路。

公开(公告)号：US5854795A

公开(公告)日：1998-12-29

申请号：US801919

申请日：1997-02-14

申请人： Yuichi Osano

发明人： Yuichi Osano

IPC分类号： G06F12/16 ,  G06F11/22 ,  G06F12/06 ,  G11C29/08 ,  G11C29/00

CPC分类号： G06F11/2247 ,  G11C29/08

摘要： A memory capacity test method capable of confirming the memory capacity of an actually mounted memory in a short time in a memory system which mounts a memory only on a portion of a memory space. The method writes first data to a check address which is an n-th power of two, and then second data to the address 0, where the second data differs from the first data, and decides that the memory is not mounted on the check address if the data read from the check address disagrees with the first data. This is based on the fact that the check address actually points the address 0 when the memory is not mounted on the check address of the nth power of two, and hence the second data is written over the first data on the address 0 in that case.

摘要翻译： 一种存储器容量测试方法，其能够在仅将存储器仅在存储器空间的一部分上安装存储器的存储器系统中在短时间内确认实际安装的存储器的存储器容量。 该方法将第一数据写入检查地址，该检查地址是二次的第二次，然后将第二数据写入地址0，其中第二数据与第一数据不同，并且确定存储器未被安装在检查地址 如果从检查地址读取的数据不符合第一个数据。 这是基于以下事实：当存储器未被安装在二次的第n个功率的检查地址上时，检查地址实际上指向地址0，因此在这种情况下第二数据被写入地址0上的第一数据 。

公开(公告)号：US5305242A

公开(公告)日：1994-04-19

申请号：US67920

申请日：1993-05-27

申请人： Noriyoshi Kikuchi ,  Masayuki Suetomi

发明人： Noriyoshi Kikuchi ,  Masayuki Suetomi

IPC分类号： G01R23/16 ,  G05F1/00 ,  H02J3/00 ,  G06J1/00

CPC分类号： G01R23/16

摘要： An AC power supply apparatus for obtaining sampled data required for the FFT (Fast Fourier Transformation) by an A/D converter. Since a clock pulse train for forming an output voltage (power supply output) is used as sample clock pulses, sampled data associated with exactly one period can be obtained. This eliminates the need for the window processing. This makes it possible to provide a low cost, error-free apparatus.

摘要翻译： 一种AC电源装置，用于通过A / D转换器获得FFT（快速傅里叶变换）所需的采样数据。 由于用于形成输出电压（电源输出）的时钟脉冲串用作采样时钟脉冲，因此可以获得与正好一个周期相关联的采样数据。 这消除了窗口处理的需要。 这使得可以提供低成本，无错误的装置。

公开(公告)号：US5132552A

公开(公告)日：1992-07-21

申请号：US743789

申请日：1991-08-12

申请人： Takeshi Ito ,  Yuji Fujita

发明人： Takeshi Ito ,  Yuji Fujita

IPC分类号： H03M1/66 ,  G06G7/30 ,  H03H11/12

CPC分类号： G06G7/30

摘要： A linear interpolator comprising an amplifier, an integrator for integrating an output of the amplifier, a feedback circuit connected between the amplifier and the integrator for bootstrapping an input voltage of the amplifier by an output voltage from the integrator, and a switch for periodically supplying a staircase input signal to the amplifier. A linearly interpolated output is derived from the integrator. The discrete input signal changing stepwise can be linearly interpolated with high accuracy.

摘要翻译： 一种线性内插器，包括放大器，用于对放大器的输出进行积分的积分器，连接在放大器和积分器之间的反馈电路，用于通过来自积分器的输出电压自举放大器的输入电压;以及开关，用于周期性地提供 楼梯输入信号到放大器。 从积分器得到线性内插输出。 离散输入信号逐步变化可以高精度线性内插。

公开(公告)号：US5515457A

公开(公告)日：1996-05-07

申请号：US756055

申请日：1991-09-06

申请人： Yuuichi Osano

发明人： Yuuichi Osano

IPC分类号： G01R13/20 ,  G06F17/17 ,  G09G5/36 ,  H03H17/00 ,  H03H17/02 ,  G06K9/36

CPC分类号： G06F17/17

摘要： Sampled points are connected by lines to form a line pattern which may have a steady portion and a suddenly changing portion. Various line patterns are classified into several classes depending on rates of change of slopes of the line patterns. When a line pattern transits from the steady portion to the suddenly changing portion, or vice versa, before or after a sampled point, the differential coefficient of an interpolation curve at the sampling point is made closer to the slope in the steady portion. Sampled signals having sudden transitions can thereby be interpolated without undue fluctuations before and after the transitions.

摘要翻译： 采样点通过线连接以形成可以具有稳定部分和突然变化部分的线图案。 根据线路图形的斜率的变化率，各种线路图案被分成几类。 当线状图案从稳定部分转移到突然变化部分，反之亦然时，在采样点之前或之后，使采样点处的内插曲线的微分系数更接近于稳定部分中的斜率。 因此，可以在转换之前和之后插入具有突变的采样信号，而不会产生不必要的波动。

公开(公告)号：US5262681A

公开(公告)日：1993-11-16

申请号：US026640

申请日：1993-03-05

申请人： Takuya Takeda

发明人： Takuya Takeda

IPC分类号： G01R13/32 ,  H03K17/62 ,  H03K17/76

CPC分类号： G01R13/32 ,  H03K17/6257

摘要： A trigger source switching circuit including a first switch system for a high frequency region, and a second switch system for a low frequency region. The first switch system is composed of a plurality of semiconductor switches having good frequency and isolation characteristics, and the adverse effect of the DC shift is eliminated by using a capacitor connected between the outputs of the semiconductor switches and the output terminal of the trigger source switching circuit. The second switch system for the low frequency region is composed of analog switches, and the output terminal of each analog switch is connected to an input terminal of an operational amplifier of a small output offset, thereby reducing the effect of the on-resistance of the analog switches and the adverse effect of the DC shift. The analog switches can be used because the frequency and isolation characteristics required in the high frequency region are unnecessary in the low frequency region.

摘要翻译： 一种触发源切换电路，包括用于高频区域的第一开关系统和用于低频区域的第二开关系统。 第一开关系统由具有良好的频率和隔离特性的多个半导体开关组成，并且通过使用连接在半导体开关的输出端和触发源开关的输出端之间的电容器来消除DC偏移的不利影响 电路。 用于低频区域的第二开关系统由模拟开关组成，每个模拟开关的输出端连接到输出偏移较小的运算放大器的输入端，从而降低了导通电阻的影响 模拟开关和直流偏移的不利影响。 可以使用模拟开关，因为在低频区域中不需要高频区域所需的频率和隔离特性。