PIXEL ARRANGEMENT AND METHOD FOR OPERATING A PIXEL ARRANGEMENT

    公开(公告)号:US20240357254A1

    公开(公告)日:2024-10-24

    申请号:US18681753

    申请日:2022-08-10

    IPC分类号: H04N25/77

    CPC分类号: H04N25/77

    摘要: In an embodiment a pixel arrangement includes a photodiode, a circuit node, a transfer transistor coupled to the photodiode and to the circuit node, an amplifier with an input coupled to the circuit node, a first capacitor and a second capacitor, a first transistor coupled to an output of the amplifier and to the first capacitor, a second transistor coupled to the first transistor and to the second capacitor, a supply terminal, a reset transistor coupled to the supply terminal, a coupling transistor coupled to the circuit node and to the reset transistor and a third capacitor with a first electrode coupled to a node between the reset transistor and the coupling transistor.

    SELF CALIBRATING BARRIER MODULATION PIXEL
    5.
    发明公开

    公开(公告)号:US20240340547A1

    公开(公告)日:2024-10-10

    申请号:US18681721

    申请日:2022-08-10

    摘要: In an embodiment a method for operating a pixel arrangement includes, during an exposure period, accumulating, by a photodetector, in a first integration period, charge carriers, pulsing, at an end of the first integration period, a transfer transistor to a first voltage level for transferring a portion of the accumulated charge carriers to a diffusion node, wherein the portion is configured to be drained to a supply voltage, continuing, by the photodetector, to accumulate, in a second integration period, charge carriers, after the second integration period, pulsing the transfer transistor to a respective further voltage level with at least one additional pulse, wherein, with each additional pulse, an additional portion of the accumulated charge carriers is configured to be drained to the supply voltage, and wherein each additional pulse is followed by an additional continued accumulation of charge carriers in a respective additional integration period with the photodetector.

    SELF CALIBRATING BARRIER MODULATION PIXEL

    公开(公告)号:US20230051657A1

    公开(公告)日:2023-02-16

    申请号:US17818962

    申请日:2022-08-10

    摘要: In an embodiment a pixel arrangement includes a photodetector configured to accumulate charge carriers by converting electromagnetic radiation, a transfer transistor electrically coupled to the photodetector, a diffusion node electrically coupled to the transfer transistor, a reset transistor electrically coupled to the diffusion node and to a pixel supply voltage and a sample-and-hold stage including at least a first capacitor and a second capacitor, an input of the sample-and-hold stage being electrically coupled to the diffusion node via an amplifier, wherein the transfer transistor is configured to be pulsed to different voltage levels for transferring parts of the accumulated charge carriers to the diffusion node, wherein at least the second capacitor is configured to store a low conversion gain signal representing a first part of the accumulated charge carriers, and wherein the first capacitor is configured to store a high conversion gain signal representing a remaining part of the accumulated charge carriers.

    PIXEL ARRANGEMENT, IMAGE SENSOR AND METHOD OF OPERATING A PIXEL ARRANGEMENT

    公开(公告)号:US20230049844A1

    公开(公告)日:2023-02-16

    申请号:US17818938

    申请日:2022-08-10

    摘要: In an embodiment a pixel arrangement includes at least one photodiode configured to convert electromagnetic radiation into a respective charge signal, a transfer gate between the photodiode and a capacitance for transferring the respective charge signal to the capacitance, a reset gate electrically coupled to the capacitance, the reset gate configured to reset the capacitance, an amplifier electrically connected to the capacitance and configured to generate, based on the respective charge signal and on a sensitivity mode, a respective amplified signal being a low sensitivity signal or a high sensitivity signal, respectively, wherein the low sensitivity signal and the high sensitivity signal are based on a common noise level, a first capacitor configured to store the high sensitivity signal, a second capacitor configured to store the low sensitivity signal, a first switch between an output terminal of the amplifier and the first capacitor and a second switch between the output terminal of the amplifier and the second capacitor.