公开(公告)号：US08307268B2

公开(公告)日：2012-11-06

申请号：US12329581

申请日：2008-12-06

申请人： Panu Chaichanavong ,  Nedeljko Varnica ,  Nitin Nangare ,  Gregory Burd ,  Zining Wu

发明人： Panu Chaichanavong ,  Nedeljko Varnica ,  Nitin Nangare ,  Gregory Burd ,  Zining Wu

IPC分类号： G06F11/00

CPC分类号： H03M13/41 ,  G11B20/1426 ,  G11B20/1803 ,  G11B2020/10759 ,  G11B2020/1457 ,  H03M13/09 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1114 ,  H03M13/13 ,  H03M13/29 ,  H03M13/2948 ,  H03M13/3746 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561

摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

摘要翻译： 提供了系统和方法，用于改进迭代解码器系统的设计和性能。 在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。 在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。 在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。 在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行1 /（1 + D）个预编码器。 一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。 这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器对编码信息施加的RLL约束。

公开(公告)号：US08312354B1

公开(公告)日：2012-11-13

申请号：US12336280

申请日：2008-12-16

申请人： Nedeljko Varnica ,  Nitin Nangare ,  Gregory Burd ,  Zining Wu

发明人： Nedeljko Varnica ,  Nitin Nangare ,  Gregory Burd ,  Zining Wu

IPC分类号： H03M13/45

CPC分类号： H03M13/6331 ,  H03M13/1105 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/4138

摘要： Systems and methods for improving the performance of iterative decoders on various channels with memory are disclosed. These systems and methods may reduce the frequency or number of situations in which the iterative decoder cannot produce decoded data that matches the data that was originally sent in a communications or data storage system. The iterative decoder includes a SISO channel detector and an ECC decoder and decodes the coded information according to at least one iterative decoding algorithm in regular decoding mode and/or at least one iterative decoding algorithm in error-recovery mode.

摘要翻译： 公开了用于改善具有存储器的各种通道上的迭代解码器的性能的系统和方法。 这些系统和方法可以减少迭代解码器不能产生与最初在通信或数据存储系统中发送的数据匹配的解码数据的情况的频率或数量。 迭代解码器包括SISO信道检测器和ECC解码器，并且按照常规解码模式中的至少一个迭代解码算法和/或错误恢复模式中的至少一个迭代解码算法解码编码信息。

公开(公告)号：US08136016B1

公开(公告)日：2012-03-13

申请号：US12263235

申请日：2008-10-31

申请人： Zining Wu ,  Gregory Burd ,  Nitin Nangare

发明人： Zining Wu ,  Gregory Burd ,  Nitin Nangare

IPC分类号： H03M13/00

CPC分类号： H03M13/373 ,  G11B20/10046 ,  G11B20/1217 ,  G11B2020/1282 ,  G11B2220/2516 ,  H03M13/00

摘要： Reproduction of encoded data which includes a split-mark. FIR data corresponding to split-mark and FIR data affected by the split-mark due to inter-symbol-interference are identified. FIR data corresponding to the split-mark is removed from the received FIR data. Recovered data is created by removing incorrect inter-symbol-interference from the FIR data due to the split-mark, and adding correct inter-symbol-interference from codeword bits. The recovered data is stitched together with data unaffected by split-mark data.

公开(公告)号：US08441750B1

公开(公告)日：2013-05-14

申请号：US13610468

申请日：2012-09-11

申请人： Nitin Nangare ,  Gregory Burd ,  Zining Wu

发明人： Nitin Nangare ,  Gregory Burd ,  Zining Wu

IPC分类号： G11B5/09 ,  G11B5/035

CPC分类号： G11B5/012 ,  G11B5/09 ,  G11B5/4886 ,  G11B20/10009 ,  G11B2220/2516

摘要： A storage controller includes a device controller and a read data channel. The read data channel includes a decoder for decoding output of a detector, where the detector is for reading data requested from a storage medium by the device controller, and the storage medium has a plurality of tracks of data thereon. When the device controller requests data from a current track of data on the storage device, the detector reads an adjacent track of data, the decoder decodes data from the adjacent track of data, the detector reads data from the current track, and the decoder decodes the data read from the current track, based on the decoded and stored data from the adjacent track of data. A storage system includes a storage medium having a plurality of tracks of data thereon and a storage controller as described above.

摘要翻译： 存储控制器包括设备控制器和读取数据通道。 读取数据通道包括用于解码检测器的输出的解码器，其中检测器用于从设备控制器读取从存储介质请求的数据，并且存储介质上有多条数据轨迹。 当设备控制器从存储设备上的当前数据轨道请求数据时，检测器读取相邻的数据轨道，解码器从相邻的数据轨道解码数据，检测器从当前轨道读取数据，并且解码器解码 基于来自相邻轨道的数据的解码和存储的数据从当前轨道读取的数据。 存储系统包括其上具有多条数据轨道的存储介质和如上所述的存储控制器。

公开(公告)号：US08395858B1

公开(公告)日：2013-03-12

申请号：US13285772

申请日：2011-10-31

申请人： Ke Han ,  Nitin Nangare ,  Zining Wu ,  Gregory Burd ,  Michael Madden

发明人： Ke Han ,  Nitin Nangare ,  Zining Wu ,  Gregory Burd ,  Michael Madden

IPC分类号： G11B5/09 ,  G11B5/035

CPC分类号： G11B20/1403 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10231 ,  G11B20/10527 ,  G11B2020/1062 ,  G11B2020/10685 ,  G11B2020/1232 ,  G11B2020/1287 ,  G11B2220/2516

摘要： Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.

摘要翻译： 提供了使用频率和相位估计来执行内插定时恢复的方法和装置。 表示扇区的模拟信号被异步采样并存储在存储设备中。 重新定时电路读取存储的采样，并且基于扇区的第一和第二定时部分的第一部分来确定相位调整。 重新定时电路产生表示在调整阶段的采样的信号，并且基于产生的信号和第一和第二定时部分的第二部分来确定采样位移调整。 重新定时电路基于样本移位调整和相位调整来计算缓冲器中扇区的起始和终止索引。 开始和结束索引可用于计算频率估计。 频率估计和相位调整用于在适当的频率和相位内插异步采样。

公开(公告)号：US08300339B1

公开(公告)日：2012-10-30

申请号：US12882802

申请日：2010-09-15

申请人： Nitin Nangare ,  Gregory Burd ,  Zining Wu

发明人： Nitin Nangare ,  Gregory Burd ,  Zining Wu

IPC分类号： G11B5/09 ,  G11B5/035

CPC分类号： G11B5/012 ,  G11B5/09 ,  G11B5/4886 ,  G11B20/10009 ,  G11B2220/2516

摘要： A storage controller includes a device controller and a read data channel. The read data channel includes a decoder for decoding output of a detector, where the detector is for reading data requested from a storage medium by the device controller, and the storage medium has a plurality of tracks of data thereon. When the device controller requests data from a current track of data on the storage device, the detector reads an adjacent track of data, the decoder decodes data from the adjacent track of data, the detector reads data from the current track, and the decoder decodes the data read from the current track, based on the decoded and stored data from the adjacent track of data. A storage system includes a storage medium having a plurality of tracks of data thereon and a storage controller as described above.

摘要翻译： 存储控制器包括设备控制器和读取数据通道。 读取数据通道包括用于解码检测器的输出的解码器，其中检测器用于从设备控制器读取从存储介质请求的数据，并且存储介质上有多条数据轨迹。 当设备控制器从存储设备上的当前数据轨道请求数据时，检测器读取相邻的数据轨道，解码器从相邻的数据轨道解码数据，检测器从当前轨道读取数据，并且解码器解码 基于来自相邻轨道的数据的解码和存储的数据从当前轨道读取的数据。 存储系统包括其上具有多条数据轨道的存储介质和如上所述的存储控制器。

公开(公告)号：US08049983B1

公开(公告)日：2011-11-01

申请号：US12323247

申请日：2008-11-25

申请人： Ke Han ,  Nitin Nangare ,  Zining Wu ,  Gregory Burd ,  Michael Madden

发明人： Ke Han ,  Nitin Nangare ,  Zining Wu ,  Gregory Burd ,  Michael Madden

IPC分类号： G11B5/09 ,  G11B5/035

CPC分类号： G11B20/1403 ,  G11B20/10009 ,  G11B20/10037 ,  G11B20/10046 ,  G11B20/10222 ,  G11B20/10231 ,  G11B20/10527 ,  G11B2020/1062 ,  G11B2020/10685 ,  G11B2020/1232 ,  G11B2020/1287 ,  G11B2220/2516

摘要： Methods and apparatus are provided for performing interpolated timing recovery using a frequency and phase estimate. An analog signal representing a sector is asynchronously sampled and stored in a storage device. A retiming circuit reads the stored samples and, based on first portions of first and second timing portions of the sector, determines phase adjustments. The retiming circuit generates a signal representing the samples at the adjusted phase and determines sample shift adjustments based on the generated signal and second portions of the first and second timing portions. The retiming circuit computes start and end indices of the sector in the buffer based on the sample shift adjustment and phase adjustment. The start and end indices may be used to compute a frequency estimate. The frequency estimate and a phase adjustment is used to interpolate the asynchronous samples at the appropriate frequency and phase.

摘要翻译： 提供了使用频率和相位估计来执行内插定时恢复的方法和装置。 表示扇区的模拟信号被异步采样并存储在存储设备中。 重新定时电路读取存储的采样，并且基于扇区的第一和第二定时部分的第一部分来确定相位调整。 重新定时电路产生表示在调整阶段的采样的信号，并且基于产生的信号和第一和第二定时部分的第二部分来确定采样位移调整。 重新定时电路基于样本移位调整和相位调整来计算缓冲器中扇区的起始和终止索引。 开始和结束索引可用于计算频率估计。 频率估计和相位调整用于在适当的频率和相位内插异步采样。

公开(公告)号：US20090150746A1

公开(公告)日：2009-06-11

申请号：US12329581

申请日：2008-12-06

申请人： Panu Chaichanavong ,  Nedeljko Varnica ,  Nitin Nangare ,  Gregory Burd ,  Zining Wu

发明人： Panu Chaichanavong ,  Nedeljko Varnica ,  Nitin Nangare ,  Gregory Burd ,  Zining Wu

IPC分类号： H03M13/05 ,  G06F11/07

CPC分类号： H03M13/41 ,  G11B20/1426 ,  G11B20/1803 ,  G11B2020/10759 ,  G11B2020/1457 ,  H03M13/09 ,  H03M13/1105 ,  H03M13/1111 ,  H03M13/1114 ,  H03M13/13 ,  H03M13/29 ,  H03M13/2948 ,  H03M13/3746 ,  H03M13/4146 ,  H03M13/6343 ,  H03M13/6502 ,  H03M13/6561

摘要： Systems and methods are provided for improved designs and performance for iterative decoder systems. In some embodiments, the iterative decoder may be decoupled from FIR samples through an FIR RAM, thus resulting in a less complex design and shorter processing times. In some embodiments, an intermediate memory may be used when passing information between the SOVA and LDPC of the iterative decoder. In some embodiments, the SOVA-required information may be continuously serialized from information received from the LDPC during each LDPC iteration. In some embodiments, the 1/(1+D2) precoder of the HR RLL encoder may be split into two serial, 1/(1+D) precoders. One 1/(1+D) precoder may be pulled outside of the HR RLL encoder and used in conjunction with the iterative decoder. This may allow for a 1/(1+D) precoder that may be used with the iterative decoder while maintaining the RLL constraints imposed upon the encoded information by the HR RLL encoder.

摘要翻译： 提供了系统和方法，用于改进迭代解码器系统的设计和性能。 在一些实施例中，迭代解码器可以通过FIR RAM从FIR样本去耦，从而导致较不复杂的设计和较短的处理时间。 在一些实施例中，当在迭代解码器的SOVA和LDPC之间传递信息时，可以使用中间存储器。 在一些实施例中，可以在每次LDPC迭代期间从从LDPC接收的信息中连续序列化所需的SOVA信息。 在一些实施例中，HR RLL编码器的1 /（1 + D2）预编码器可以被分成两个串行，1 /（1 + D）个预编码器。 一个1 /（1 + D）预编码器可以被拉出HR RLL编码器外部并与迭代解码器结合使用。 这可以允许可以与迭代解码器一起使用的1 /（1 + D）预编码器，同时保持由HR RLL编码器对编码信息施加的RLL约束。

公开(公告)号：US08321763B1

公开(公告)日：2012-11-27

申请号：US13410068

申请日：2012-03-01

申请人： Zining Wu ,  Gregory Burd ,  Nitin Nangare

发明人： Zining Wu ,  Gregory Burd ,  Nitin Nangare

IPC分类号： H03M13/00

CPC分类号： H03M13/373 ,  G11B20/10046 ,  G11B20/1217 ,  G11B2020/1282 ,  G11B2220/2516 ,  H03M13/00

摘要： Reproduction of encoded data which includes a split-mark. FIR data corresponding to split-mark and FIR data affected by the split-mark due to inter-symbol-interference are identified. FIR data corresponding to the split-mark is removed from the received FIR data. Recovered data is created by removing incorrect inter-symbol-interference from the FIR data due to the split-mark, and adding correct inter-symbol-interference from codeword bits. The recovered data is stitched together with data unaffected by split-mark data.

摘要翻译： 包含分割标记的编码数据的再现。 识别对应于分割标记的FIR数据和由于符号间干扰而受分割影响的FIR数据。 对应于分割标记的FIR数据从接收到的FIR数据中去除。 通过从分离标记去除来自FIR数据的不正确的符号间干扰，并从码字比特中添加正确的符号间干扰，创建恢复的数据。 恢复的数据与不受分割标记数据影响的数据进行缝合。

公开(公告)号：US08122314B1

公开(公告)日：2012-02-21

申请号：US11936418

申请日：2007-11-07

申请人： Shaohua Yang ,  Nedeljko Varnica ,  Nitin Nangare ,  Zining Wu

发明人： Shaohua Yang ,  Nedeljko Varnica ,  Nitin Nangare ,  Zining Wu

IPC分类号： H03M13/00 ,  H04L1/18 ,  G06F11/00

CPC分类号： H04L1/0054 ,  H03M13/2987 ,  H03M13/4138 ,  H03M13/6331 ,  H04L1/005 ,  H04L1/0065 ,  H04L1/0071

摘要： In iterative decoding, a data recovery scheme corrects for corrupted or defective data by incorporating results from a previous decoding iteration. In one embodiment, a final multiplexer selects between the final detector output or a previous detector output based on the absence or presence of defective data. In another embodiment, the branch metrics for the defective data, which otherwise would be combined with a priori LLRs from an outer decoder of a prior stage, are ignored so that the a priori LLRs themselves are used alone. The two embodiments can be used together.

摘要翻译： 在迭代解码中，数据恢复方案通过结合先前的解码迭代的结果来校正损坏的或有缺陷的数据。 在一个实施例中，最终多路复用器根据不存在或存在缺陷数据在最终检测器输出或先前检测器输出之间进行选择。 在另一个实施例中，将忽略否则将与来自前一级的外部解码器的先验LLR组合的缺陷数据的分支量度，以使得单独使用先验LLR本身。 两个实施例可以一起使用。