公开(公告)号：US08861229B2

公开(公告)日：2014-10-14

申请号：US12129039

申请日：2008-05-29

申请人： Donald E. Alfano ,  Timothy J. Dupuis ,  Zhiwei Dong ,  Brett E. Etter

发明人： Donald E. Alfano ,  Timothy J. Dupuis ,  Zhiwei Dong ,  Brett E. Etter

IPC分类号： H02M3/335 ,  H02M3/156

CPC分类号： H03K17/691 ,  H03K17/7955

摘要： An apparatus includes a regulator circuit that generates a voltage in response to an input current being supplied to an input terminal and functional circuitry, powered by the voltage generated by the regulator circuit. The functional circuitry, e.g., an oscillator, generates a signal using the generated voltage, the signal indicative that the current is being supplied to the apparatus. The signal can be provided over an isolation link to provide a control signal for controlling a high voltage driver circuit.

摘要翻译： 一种装置包括调节器电路，其响应于输入电流产生电压，该输入电流被提供给由调节器电路产生的电压供电的输入端子和功能电路。 功能电路，例如振荡器，使用所产生的电压产生信号，该信号指示电流被提供给设备。 信号可以通过隔离链路提供，以提供用于控制高电压驱动器电路的控制信号。

公开(公告)号：US20110050198A1

公开(公告)日：2011-03-03

申请号：US12551788

申请日：2009-09-01

申请人： Zhiwei Dong ,  William W. K. Tang ,  Axel Thomsen

发明人： Zhiwei Dong ,  William W. K. Tang ,  Axel Thomsen

IPC分类号： G05F3/16

CPC分类号： G05F3/242 ,  G05F1/607

摘要： A technique for reducing power dissipation and circuit area for a high voltage application includes creating a low-voltage, local power supply for use with local circuitry. In at least one embodiment of the invention, an apparatus includes an output node configured to provide a regulated output voltage. The apparatus includes a variable current source coupled to a first power supply node, wherein the variable current source is configured to provide an output current to the output node based on a control signal on a control node. The apparatus includes a feedback circuit configured to generate the control signal based on a mirrored current. The mirrored current is a mirrored version of a residual current flowing between the output node and a second power supply node. The regulated output voltage has a voltage level less than the voltage level on the first power supply node.

摘要翻译： 用于降低功率耗散和高电压应用的电路面积的技术包括产生用于本地电路的低电压本地电源。 在本发明的至少一个实施例中，一种装置包括被配置成提供调节输出电压的输出节点。 该装置包括耦合到第一电源节点的可变电流源，其中可变电流源被配置为基于控制节点上的控制信号向输出节点提供输出电流。 该装置包括被配置为基于镜像电流产生控制信号的反馈电路。 镜像电流是在输出节点和第二电源节点之间流动的剩余电流的镜像版本。 调节输出电压具有小于第一电源节点上的电压电平的电压电平。

公开(公告)号：US20120241905A1

公开(公告)日：2012-09-27

申请号：US13072293

申请日：2011-03-25

申请人： William W.K. Tang ,  Shouli Yan ,  Zhiwei Dong

发明人： William W.K. Tang ,  Shouli Yan ,  Zhiwei Dong

IPC分类号： H01L29/92 ,  H01L21/02

CPC分类号： H01L28/40 ,  H01L21/76 ,  H01L23/5223 ,  H01L27/0207 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a conductive substrate pick-up region in the substrate that forms a perimeter around a portion of the substrate. Conductive stripes traverse the portion of the substrate within the perimeter and are coupled to a low impedance node along with the substrate pick-up region. A capacitor has a bottom plate formed above the conductive stripes. The pick-up region and the conductive stripes absorb injected current caused by parasitic capacitance between the bottom plate of the capacitor and the substrate region thereby reducing cross-talk caused by the injected current.

摘要翻译： 集成电路包括在衬底中形成围绕衬底的一部分的周边的导电衬底拾取区域。 导电条纹遍及周边的衬底部分，并与衬底拾取区域一起耦合到低阻抗节点。 电容器具有形成在导电条上的底板。 拾取区域和导电条纹吸收由电容器的底板和衬底区域之间的寄生电容引起的注入电流，从而减少由注入电流引起的串扰。

公开(公告)号：US07019586B2

公开(公告)日：2006-03-28

申请号：US10806630

申请日：2004-03-23

申请人： Zhiwei Dong

发明人： Zhiwei Dong

IPC分类号： H03K5/00

CPC分类号： H03H11/0472 ,  H03J1/0008 ,  H03J3/08 ,  H03J2200/02 ,  H03J2200/28

摘要： A technique to achieve high-speed tuning of a Gm-C circuit, such as, for example, a Gm-C filter. In one embodiment, a master Gm-C time-constant circuit incorporates at least one element (either a transconductance or a capacitance) that is matched to a corresponding element (transconductance or capacitance) in the (slave) Gm-C circuit. A waveform generated by the master Gm-C time-constant circuit is used to control a sampler. In one embodiment, the sampler samples a precision counter so as to result in a sampler output having a polarity that steers the tuning voltage in the necessary direction. A tuning control stage coupled to the sampler output implements an algorithm that causes the tuning voltage to converge, with a predetermined precision, to the desired tuning voltage.

摘要翻译： 实现Gm-C电路的高速调谐的技术，例如Gm-C滤波器。 在一个实施例中，主Gm-C时间常数电路包括与（从）Gm-C电路中的相应元件（跨导或电容）匹配的至少一个元件（跨导或电容）。 由主Gm-C时间常数电路产生的波形用于控制采样器。 在一个实施例中，采样器对精度计数器进行采样，以产生具有在所需方向上调整调谐电压的极性的采样器输出。 耦合到采样器输出的调谐控制级实现了使调谐电压以预定精度收敛到期望的调谐电压的算法。

公开(公告)号：US20050212590A1

公开(公告)日：2005-09-29

申请号：US10806630

申请日：2004-03-23

申请人： Zhiwei Dong

发明人： Zhiwei Dong

IPC分类号： H03B1/00 ,  H03H11/12 ,  H03J1/00 ,  H03J3/08

CPC分类号： H03H11/0472 ,  H03J1/0008 ,  H03J3/08 ,  H03J2200/02 ,  H03J2200/28

摘要： A technique to achieve high-speed tuning of a Gm-C circuit, such as, for example, a Gm-C filter. In one embodiment, a master Gm-C time-constant circuit incorporates at least one element (either a transconductance or a capacitance) that is matched to a corresponding element (transconductance or capacitance) in the (slave) Gm-C circuit. A waveform generated by the master Gm-C time-constant circuit is used to control a sampler. In one embodiment, the sampler samples a precision counter so as to result in a sampler output having a polarity that steers the tuning voltage in the necessary direction. A tuning control stage coupled to the sampler output implements an algorithm that causes the tuning voltage to converge, with a predetermined precision, to the desired tuning voltage.

摘要翻译： 实现Gm-C电路的高速调谐的技术，例如Gm-C滤波器。 在一个实施例中，主Gm-C时间常数电路包括与（从）Gm-C电路中的相应元件（跨导或电容）匹配的至少一个元件（跨导或电容）。 由主Gm-C时间常数电路产生的波形用于控制采样器。 在一个实施例中，采样器对精度计数器进行采样，以产生具有在所需方向上调整调谐电压的极性的采样器输出。 耦合到采样器输出的调谐控制级实现了使调谐电压以预定精度收敛到期望的调谐电压的算法。

公开(公告)号：US08644365B2

公开(公告)日：2014-02-04

申请号：US13435179

申请日：2012-03-30

申请人： Zhiwei Dong

发明人： Zhiwei Dong

IPC分类号： H04B1/38

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1204 ,  H01L2224/45099 ,  H01L2924/00

摘要： In one embodiment, a method includes receiving an input signal in transmitter circuitry of a first semiconductor die and processing the input signal, sending the processed input signal to an isolation circuit of the die to generate a voltage isolated signal, and outputting the voltage isolated signal from the isolation circuit to a second semiconductor die coupled to the first semiconductor die via a bonding mechanism. Note that this second semiconductor die may not include isolation circuitry.

摘要翻译： 在一个实施例中，一种方法包括在第一半导体管芯的发射器电路中接收输入信号并处理输入信号，将经处理的输入信号发送到管芯的隔离电路以产生电压隔离信号，并输出电压隔离信号 从隔离电路经由接合机构耦合到第一半导体管芯的第二半导体管芯。 注意，该第二半导体管芯可以不包括隔离电路。

公开(公告)号：US20130001738A1

公开(公告)日：2013-01-03

申请号：US13174390

申请日：2011-06-30

申请人： Zhiwei Dong

发明人： Zhiwei Dong

IPC分类号： H01L29/06

CPC分类号： H01L23/49575 ,  H01L23/522 ,  H01L23/5223 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： A high breakdown voltage integrated circuit isolator device communicates a digital signal from a signal input on one semiconductor die to a signal output on another semiconductor die while providing high voltage isolation between the signal input and the signal output. Each die may include a respective capacitive isolation barrier structure that couple together via a bonding wire between combined top metal/bonding pads of the capacitive isolation barrier structures.

摘要翻译： 高耐压集成电路隔离器装置将来自一个半导体管芯上的信号输入的数字信号传送到另一半导体管芯上的信号输出，同时在信号输入和信号输出之间提供高电压隔离。 每个管芯可以包括通过电容隔离阻挡结构的组合的顶部金属/接合焊盘之间的接合线耦合在一起的相应的电容隔离屏障结构。

公开(公告)号：US08203370B2

公开(公告)日：2012-06-19

申请号：US12494621

申请日：2009-06-30

申请人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

发明人： Shouli Yan ,  Zhiwei Dong ,  Axel Thomsen

IPC分类号： H03K3/00

CPC分类号： H03K3/3565 ,  H03K5/088

摘要： A Schmitt trigger comprises first and second circuitry. The first circuitry receives an input voltage and provides an output voltage at either a logical “low” or a logical “high” voltage level responsive to the input voltage and a first bias voltage. The second circuitry connects to the first circuitry to generate a second bias current for generating the output voltage. The second bias current is larger than the first bias current. The Schmitt trigger operates in a low power mode of operation using only the first bias voltage to maintain the logical “low” voltage level or the logical “high” voltage level at a substantially constant level. In a high power mode of operation the Schmitt trigger uses the second bias voltage during transition periods between the logical “low” voltage level and the logical “high” voltage level.

摘要翻译： 施密特触发器包括第一和第二电路。 第一电路接收输入电压并且响应于输入电压和第一偏置电压在逻辑“低”或逻辑“高”电压电平提供输出电压。 第二电路连接到第一电路以产生用于产生输出电压的第二偏置电流。 第二偏置电流大于第一偏置电流。 施密特触发器仅在第一偏置电压下工作在低功耗工作模式，以将逻辑“低”电压电平或逻辑“高”电压电平维持在基本恒定的水平。 在高功率工作模式下，施密特触发器在逻辑“低”电压电平和逻辑“高”电压电平之间的过渡期间使用第二偏置电压。

公开(公告)号：US20130257527A1

公开(公告)日：2013-10-03

申请号：US13435179

申请日：2012-03-30

申请人： Zhiwei Dong

发明人： Zhiwei Dong

IPC分类号： H01L25/065 ,  H01L27/06

CPC分类号： H01L24/49 ,  H01L24/48 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05553 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/1204 ,  H01L2224/45099 ,  H01L2924/00

摘要： In one embodiment, a method includes receiving an input signal in transmitter circuitry of a first semiconductor die and processing the input signal, sending the processed input signal to an isolation circuit of the die to generate a voltage isolated signal, and outputting the voltage isolated signal from the isolation circuit to a second semiconductor die coupled to the first semiconductor die via a bonding mechanism. Note that this second semiconductor die may not include isolation circuitry.

摘要翻译： 在一个实施例中，一种方法包括在第一半导体管芯的发射器电路中接收输入信号并处理输入信号，将经处理的输入信号发送到管芯的隔离电路以产生电压隔离信号，并输出电压隔离信号 从隔离电路经由接合机构耦合到第一半导体管芯的第二半导体管芯。 注意，该第二半导体管芯可以不包括隔离电路。

公开(公告)号：US08451032B2

公开(公告)日：2013-05-28

申请号：US12976020

申请日：2010-12-22

申请人： Zhiwei Dong ,  Ka Y. Leung

发明人： Zhiwei Dong ,  Ka Y. Leung

IPC分类号： H03B1/00 ,  H03K3/00

CPC分类号： H03K3/3565

摘要： High voltage isolation capabilities are provided using a first integrated circuit die that includes an inverting circuit path and a non-inverting circuit path coupled to receive a single-ended signal and to generate a differential signal from the single-ended signal for transmission over an isolation link. A second integrated circuit die includes a differential Schmitt trigger circuit coupled to the differential signal communicated over the isolation link and to supply at least one output signal corresponding thereto. An isolation barrier is disposed between the inverting and non-inverting circuit paths and the differential Schmitt trigger circuit and includes at least two isolation capacitors coupled to respectively transmit each portion of the differential signal.

摘要翻译： 使用第一集成电路管芯提供高电压隔离能力，所述第一集成电路管芯包括反相电路路径和非反相电路路径，所述反相电路路径和非反相电路路径被耦合以接收单端信号并从单端信号产生差分信号以通过隔离传输 链接。 第二集成电路管芯包括与通过隔离链路传送的差分信号耦合的差分施密特触发器电路，并提供与其对应的至少一个输出信号。 隔离屏障设置在反相和非反相电路路径和差分施密特触发电路之间，并且包括耦合以分别传输差分信号的每个部分的至少两个隔离电容器。