Data encoding methods and circuits
    1.
    发明申请
    Data encoding methods and circuits 失效
    数据编码方法和电路

    公开(公告)号:US20050238246A1

    公开(公告)日:2005-10-27

    申请号:US10983805

    申请日:2004-11-08

    Abstract: A data encoding method. First, a data array comprising a plurality of elements is stored in a memory. The number of elements unequal to a predetermined value is counted while elements of the array are stored in the memory. Then, a control module reads elements from the data array, and determines whether the number of read elements unequal to the predetermined value is equal to the counted number. When the number of read elements unequal to the predetermined value is equal to the counted number, the control module stops reading elements from the data array.

    Abstract translation: 数据编码方法。 首先,将包括多个元素的数据阵列存储在存储器中。 计数不等于预定值的元素的数量,同时将数组的元素存储在存储器中。 然后,控制模块从数据阵列中读取元件,并且确定不等于预定值的读取元素的数量是否等于计数的数量。 当不等于预定值的读取元件的数量等于计数的数量时,控制模块停止从数据数组中读取元件。

    Data encoding methods and circuits
    2.
    发明授权
    Data encoding methods and circuits 失效
    数据编码方法和电路

    公开(公告)号:US07388991B2

    公开(公告)日:2008-06-17

    申请号:US10983805

    申请日:2004-11-08

    Abstract: A data encoding method. First, a data array comprising a plurality of elements is stored in a memory. The number of elements unequal to a predetermined value is counted while elements of the array are stored in the memory. Then, a control module reads elements from the data array, and determines whether the number of read elements unequal to the predetermined value is equal to the counted number. When the number of read elements unequal to the predetermined value is equal to the counted number, the control module stops reading elements from the data array.

    Abstract translation: 数据编码方法。 首先,将包括多个元素的数据阵列存储在存储器中。 计数不等于预定值的元素的数量,同时将数组的元素存储在存储器中。 然后,控制模块从数据阵列中读取元件,并且确定不等于预定值的读取元素的数量是否等于计数的数量。 当不等于预定值的读取元件的数量等于计数的数量时,控制模块停止从数据数组中读取元件。

    Method and apparatus to reduce the system load of motion estimation for DSP
    3.
    发明授权
    Method and apparatus to reduce the system load of motion estimation for DSP 有权
    降低DSP运动估计系统负载的方法和装置

    公开(公告)号:US07274824B2

    公开(公告)日:2007-09-25

    申请号:US10249440

    申请日:2003-04-10

    CPC classification number: G06F17/16 G06T7/223 G06T2200/28 H04N19/43 H04N19/61

    Abstract: A method and apparatus to reduce the system load of motion estimation for DSP discloses circular buffers, a plurality of absolute difference calculation circuits, a multiple input adder, a full adder, a plurality of accumulators, and a control circuit. The first four bytes from the reference block buffer and the first four bytes from the search window buffer are sent to the four absolute difference calculation circuits. The control circuit determines which of the accumulators requires incrementing the value already in that accumulator by the current output of the multiple input adder. A new set of bytes from the search window buffer is then sent to the absolute difference calculation circuits, a new sum is calculated, and a second accumulator is incremented by the new sum. When all accumulators have been updated, new reference block data used. Each byte of data is loaded from memory only once.

    Abstract translation: 降低DSP的运动估计的系统负载的方法和装置公开了循环缓冲器,多个绝对差计算电路,多输入加法器,全加器,多个累加器和控制电路。 来自参考块缓冲器的前四个字节和来自搜索窗口缓冲器的前四个字节被发送到四个绝对差计算电路。 控制电路确定哪个累加器需要通过多输入加法器的当前输出来增加该累加器中的值。 然后将来自搜索窗口缓冲器的一组新的字节发送到绝对差分计算电路,计算新的和,并且第二累加器增加新的和。 当所有累加器都被更新时,使用新的参考块数据。 数据的每个字节从存储器加载一次。

    METHOD AND RELATED PROCESSING CIRCUITS FOR REDUCING MEMORY ACCESSING WHILE PERFORMING DE/COMPRESSING OF MULTIMEDIA FILES
    4.
    发明申请
    METHOD AND RELATED PROCESSING CIRCUITS FOR REDUCING MEMORY ACCESSING WHILE PERFORMING DE/COMPRESSING OF MULTIMEDIA FILES 失效
    用于在执行多媒体文件的压缩时减少存储器访问的方法和相关处理电路

    公开(公告)号:US20050213829A1

    公开(公告)日:2005-09-29

    申请号:US10708786

    申请日:2004-03-25

    Applicant: Heng-Kuan Lee

    Inventor: Heng-Kuan Lee

    CPC classification number: H04N19/426

    Abstract: Method and apparatus for reducing memory access while de/compressing multimedia files, videos, or image files. An image is divided into blocks, and a frequency data matrix corresponding to a frequency transformed and quantized block is stored in a memory for later de/compression. The method includes registering a bit plane containing a plurality of bits in a register module, wherein each bit represents whether a corresponding element of the data matrix equals zero. While accessing the memory for the data matrix, if a bit of the bit plane shows that its corresponding element of the data array is zero, the element is not accessed from the memory. In checking bits corresponding to elements not yet accessed; if these bits show that elements not accessed are all zero, accessing for the data array can be terminated without accessing them. Thus, memory access can be reduced to occupy less bandwidth of the memory.

    Abstract translation: 多媒体文件,视频或图像文件的解/压缩的方法和装置。 图像被划分为块,并且将与频率变换和量化块相对应的频率数据矩阵存储在存储器中用于稍后的去/压缩。 该方法包括在寄存器模块中注册包含多个位的位平面,其中每个位表示数据矩阵的相应元素是否等于零。 在访问数据矩阵的存储器时,如果位平面的位显示其数据阵列的相应元素为零,则不会从存储器访问该元素。 在检查对应于尚未访问的元素的位; 如果这些位显示未访问的元素都为零,则可以在不访问数据阵列的情况下终止对数据阵列的访问。 因此,可以减少存储器访问以占用较少的存储器带宽。

    Method and related processing circuits for reducing memory accessing while performing de/compressing of multimedia files
    5.
    发明授权
    Method and related processing circuits for reducing memory accessing while performing de/compressing of multimedia files 失效
    用于在执行多媒体文件的去/压缩期间减少存储器访问的方法和相关处理电路

    公开(公告)号:US07415161B2

    公开(公告)日:2008-08-19

    申请号:US10708786

    申请日:2004-03-25

    Applicant: Heng-Kuan Lee

    Inventor: Heng-Kuan Lee

    CPC classification number: H04N19/426

    Abstract: Method and apparatus for reducing memory access while de/compressing multimedia files, videos, or image files. An image is divided into blocks, and a frequency data matrix corresponding to a frequency transformed and quantized block is stored in a memory for later de/compression. The method includes registering a bit plane containing a plurality of bits in a register module, wherein each bit represents whether a corresponding element of the data matrix equals zero. While accessing the memory for the data matrix, if a bit of the bit plane shows that its corresponding element of the data array is zero, the element is not accessed from the memory. In checking bits corresponding to elements not yet accessed; if these bits show that elements not accessed are all zero, accessing for the data array can be terminated without accessing them. Thus, memory access can be reduced to occupy less bandwidth of the memory.

    Abstract translation: 多媒体文件,视频或图像文件的解/压缩的方法和装置。 图像被划分为块,并且将与频率变换和量化块相对应的频率数据矩阵存储在存储器中用于稍后的去/压缩。 该方法包括在寄存器模块中注册包含多个位的位平面,其中每个位表示数据矩阵的相应元素是否等于零。 在访问数据矩阵的存储器时,如果位平面的位显示其数据阵列的相应元素为零,则不会从存储器访问该元素。 在检查对应于尚未访问的元素的位; 如果这些位显示未访问的元素都为零,则可以在不访问数据阵列的情况下终止对数据阵列的访问。 因此,可以减少存储器访问以占用较少的存储器带宽。

    Error correction code circuit with reduced hardware complexity
    6.
    发明授权
    Error correction code circuit with reduced hardware complexity 失效
    纠错码电路降低硬件复杂度

    公开(公告)号:US07028247B2

    公开(公告)日:2006-04-11

    申请号:US10248188

    申请日:2002-12-25

    Applicant: Heng-Kuan Lee

    Inventor: Heng-Kuan Lee

    CPC classification number: G06F7/724 H03M13/158

    Abstract: An error correction code circuit with reduced hardware complexity is positioned inside a microprocessor. The microprocessor has a Galois field multiplier for performing a Galois field multiplication on data processed by the error correction code circuit. The error correction code circuit has a first register for storing an input data, a plurality of calculation units, a third register for storing an output data corresponding to the input data, and a controller for controlling operation of the error correction code circuit. Each calculation unit has a Galois field adder, and a second register electrically connected to the Galois field adder. The controller transmits data of each calculation unit to the same Galois field multiplier for a corresponding Galois field multiplication, and the result outputted by the Galois field multiplier is transmitted back to the error correction code circuit.

    Abstract translation: 降低硬件复杂度的纠错码电路位于微处理器的内部。 微处理器具有伽罗瓦域乘法器,用于对由纠错码电路处理的数据执行伽罗瓦域乘法。 纠错码电路具有用于存储输入数据的第一寄存器,多个计算单元,用于存储对应于输入数据的输出数据的第三寄存器,以及用于控制纠错码电路的操作的控制器。 每个计算单元具​​有伽罗瓦域加法器和与伽罗瓦域加法器电连接的第二寄存器。 控制器将每个计算单元的数据发送到相应的伽罗瓦域乘法器用于对应的伽罗瓦域乘法,并且由伽罗瓦域乘法器输出的结果被发送回纠错码电路。

    Experimental design for motion estimation
    7.
    发明授权
    Experimental design for motion estimation 失效
    运动估计实验设计

    公开(公告)号:US06993077B2

    公开(公告)日:2006-01-31

    申请号:US10065908

    申请日:2002-11-28

    Applicant: Heng-Kuan Lee

    Inventor: Heng-Kuan Lee

    CPC classification number: H04N19/53

    Abstract: An experimental design for motion estimation in video compression that reduces the number of search locations within a search window by selecting the search locations from a predefined orthogonal table. The search locations are then compared with a reference block to generate match-values that are used to generate level-values reflecting dispositional relationships of the search locations and the relative magnitudes of the match-values. A preliminary motion vector is generated according to the relative magnitudes of the level-values. Candidate results are also generated based on the match-values. A final motion vector is generated by applying predetermined formulas to the level-values and altering the preliminary motion vector according to the candidate results when indicated to do so by the results of the formulas.

    Abstract translation: 视频压缩中的运动估计的实验设计,通过从预定义的正交表中选择搜索位置来减少搜索窗口内搜索位置的数量。 然后将搜索位置与参考块进行比较以产生用于产生反映搜索位置的配置关系和匹配值的相对大小的级别值的匹配值。 根据电平值的相对幅度产生初步运动矢量。 也可以根据匹配值生成候选结果。 通过将预定公式应用于电平值并根据候选结果根据公式的结果指示来改变初步运动矢量来生成最终运动矢量。

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