公开(公告)号：US20060105528A1

公开(公告)日：2006-05-18

申请号：US11182671

申请日：2005-07-15

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减少导致跨导增益（Gm），结果是热电子效应被抑制，并且器件的可靠性增强。

公开(公告)号：US07233018B2

公开(公告)日：2007-06-19

申请号：US11182671

申请日：2005-07-15

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L29/06 ,  H01L31/00

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减小导致跨导（Gm）的增益，结果是热电子效应被抑制，并且器件的可靠性增强。

公开(公告)号：US07605039B2

公开(公告)日：2009-10-20

申请号：US11447786

申请日：2006-06-06

申请人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

摘要翻译： 提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。 晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

公开(公告)号：US08164137B2

公开(公告)日：2012-04-24

申请号：US12556666

申请日：2009-09-10

申请人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H01L29/66 ,  H01L21/02

CPC分类号： H01L29/785 ,  H01L29/66818 ,  H01L29/7851

摘要： Provided are a multiple-gate MOS (metal oxide semiconductor) transistor and a method of manufacturing the same. The transistor includes a single crystalline active region having a channel region having an upper portion of a streamlined shape (∩) obtained by patterning an upper portion of a bulk silicon substrate with an embossed pattern, and having a thicker and wider area than the channel region; a nitride layer formed at both side surfaces of the single crystalline active region to expose an upper portion of the single crystalline active region at a predetermined height; and a gate electrode formed to be overlaid with the exposed upper portion of the single crystalline active region of the channel region.

摘要翻译： 提供一种多栅极MOS（金属氧化物半导体）晶体管及其制造方法。 晶体管包括具有通道区域的单晶有源区域，沟道区域具有通过用压花图案图案化体硅衬底的上部并且具有比沟道区域更厚和更宽的面积而获得的流线型形状（∩）的上部 ; 形成在所述单晶有源区的两个侧表面处的氮化物层，以在预定高度暴露所述单晶有源区的上部; 以及形成为与通道区域的单晶有源区域的暴露的上部分重叠的栅电极。

公开(公告)号：US07759737B2

公开(公告)日：2010-07-20

申请号：US11924903

申请日：2007-10-26

申请人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： H01L27/12

CPC分类号： H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7854

摘要： Provided are a dual structure FinFET and a method of fabricating the same. The FinFET includes: a lower device including a lower silicon layer formed on a substrate and a gate electrode vertically formed on the substrate; an upper device including an upper silicon layer formed on the lower device and the vertically formed gate electrode; and a first solid source material layer, a solid source material interlayer insulating layer, and a second solid source material layer sequentially formed between the lower silicon layer and the upper silicon layer. Therefore, the FinFET can be provided which enhances the density of integration of a circuit, suppresses thin film damages due to ion implantation using solid phase material layers, and has a stabilized characteristic by a simple and low-cost process. Also, mobility of an upper device can be improved to enhance current drivability of the upper device, isolation can be implemented through a buried oxide layer to reduce an effect due to a field oxide layer, and raised source and drain can be implemented to reduce serial resistance components of the source and drain to increase current drivability.

摘要翻译： 提供了一种双重结构的FinFET及其制造方法。 FinFET包括：下部器件，包括形成在衬底上的下硅层和垂直形成在衬底上的栅电极; 上部器件，包括形成在下部器件上的上硅层和垂直形成的栅电极; 以及顺序地形成在下硅层和上硅层之间的第一固体源材料层，固体源材料层间绝缘层和第二固体源材料层。 因此，可以提供FinFET，其增强电路的集成密度，抑制由于使用固相材料层的离子注入引起的薄膜损伤，并且通过简单且低成本的工艺具有稳定的特性。 此外，可以提高上部器件的迁移率以增强上部器件的电流驱动能力，可以通过掩埋氧化物层实现隔离，以减少由于场氧化物层引起的影响，并且可以实现升高的源极和漏极以减少串联 源极和漏极的电阻分量以增加电流驱动能力。

公开(公告)号：US07709330B2

公开(公告)日：2010-05-04

申请号：US11745574

申请日：2007-05-08

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/8234

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/66659

摘要： Provided are high voltage metal oxide semiconductor field effect transistor (HVMOSFET) having a Si/SiGe heterojunction structure and method of manufacturing the same. In this method, a substrate on which a Si layer, a relaxed SiGe epitaxial layer, a SiGe epitaxial layer, and a Si epitaxial layer are stacked or a substrate on which a Si layer having a well region, a SiGe epitaxial layer, and a Si epitaxial layer are stacked is formed. For the device having the heterojunction structure, the number of conduction carriers through a potential well and the mobility of the carriers increase to reduce an on resistance, thus increasing saturation current. Also, an intensity of vertical electric field decreases so that a breakdown voltage can be maintained at a very high level. Further, a reduction in vertical electric field due to the heterojunction structure leads to a gain in transconductance (Gm), with the results that a hot electron effect is inhibited and the reliability of the device is enhanced.

摘要翻译： 提供了具有Si / SiGe异质结结构的高压金属氧化物半导体场效应晶体管（HVMOSFET）及其制造方法。 在该方法中，层叠有Si层，弛豫SiGe外延层，SiGe外延层和Si外延层的基板或其上具有阱区的Si层，SiGe外延层和 Si外延层被形成。 对于具有异质结结构的器件，通过势阱的导电载流子数量和载流子的迁移率增加，以降低导通电阻，从而增加饱和电流。 此外，垂直电场的强度降低，使得击穿电压可以保持在非常高的水平。 此外，由于异质结构造成的垂直电场的减少导致跨导增益（Gm），结果是热电子效应被抑制，并且器件的可靠性增强。

公开(公告)号：US07332774B2

公开(公告)日：2008-02-19

申请号：US11727268

申请日：2007-03-26

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L29/76 ,  H01L29/94

CPC分类号： H01L29/785 ,  H01L29/66818

摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

摘要翻译： 提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域 通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。 由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被 栅电极。 此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

公开(公告)号：US07208356B2

公开(公告)日：2007-04-24

申请号：US10989006

申请日：2004-11-16

申请人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

发明人： Young Kyun Cho ,  Sung Ku Kwon ,  Tae Moon Roh ,  Dae Woo Lee ,  Jong Dae Kim

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/785 ,  H01L29/66818

摘要： Provided is a multiple-gate metal oxide semiconductor (MOS) transistor and a method for manufacturing the same, in which a channel is implemented in a streamline shape, an expansion region is implemented in a gradually increased form, and source and drain regions is implemented in an elevated structure by using a difference of a thermal oxidation rate depending on a crystal orientation of silicon and a geographical shape of the single-crystal silicon pattern. As the channel is formed in a streamline shape, it is possible to prevent the degradation of reliability due to concentration of an electric field and current driving capability by the gate voltage is improved because the upper portion and both sides of the channel are surrounded by the gate electrodes. In addition, a current crowding effect is prevented due to the expansion region increased in size and source and drain series resistance is reduced by elevated source and drain structures, thereby increasing the current driving capability.

摘要翻译： 提供一种多栅极金属氧化物半导体（MOS）晶体管及其制造方法，其中以流线形状实现沟道，扩展区域以逐渐增加的形式实现，并且实现源极和漏极区域 通过使用取决于硅的晶体取向的热氧化速率的差异和单晶硅图案的地理形状，在升高的结构中。 由于通道形成为流线形状，所以可以防止由于电场集中引起的可靠性的劣化，由于栅极电压的电流驱动能力得到改善，因为通道的上部和两侧被 栅电极。 此外，由于扩大区域的尺寸增加，阻止了电流拥挤效应，并且通过升高的源极和漏极结构降低了源极和漏极串联电阻，从而增加了电流驱动能力。

公开(公告)号：US08150903B2

公开(公告)日：2012-04-03

申请号：US12136107

申请日：2008-06-10

申请人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

发明人： Yil Suk Yang ,  Jung Hee Suk ,  Chun Gi Lyuh ,  Tae Moon Roh ,  Jong Dae Kim

IPC分类号： G06F7/57

CPC分类号： G06F7/57 ,  G06F7/5324 ,  G06F7/5338

摘要： Provided are a reconfigurable arithmetic unit and a processor having the same. The reconfigurable arithmetic unit can perform an addition operation or a multiplication operation according to an instruction by sharing an adder. The reconfigurable arithmetic unit includes a booth encoder for encoding a multiplier, a partial product generator for generating a plurality of partial products using the encoded multiplier and a multiplicand, a Wallace tree circuit for compressing the partial products into a first partial product and a second partial product, a first Multiplexer (MUX) for selecting and outputting one of the first partial product and a first addition input according to a selection signal, a second MUX for selecting and outputting one of the second partial product and a second addition input according to the selection signal, and a Carry Propagation Adder (CPA) for adding an output of the first MUX and an output of the second MUX to output an operation result. The arithmetic unit can operate as an adder or a multiplier according to an instruction, and thus can increase the degree of use of entire hardware.

摘要翻译： 提供了一种可重构运算单元和具有该可重配置运算单元的处理器。 可重构算术单元可以通过共享加法器来执行根据指令的相加操作或乘法运算。 可重构算术单元包括用于编码乘数的展位编码器，用于使用编码乘数产生多个部分乘积的部分乘积生成器和被乘数，用于将部分乘积压缩为第一部分乘积的华莱士树电路和第二部分乘积 产品，用于根据选择信号选择和输出第一部分积和第一加法输入之一的第一多路复用器（MUX），用于根据选择信号选择和输出第二部分乘积和第二加法输入之一的第二MUX 选择信号和用于添加第一MUX的输出和第二MUX的输出的进位传播加法器（CPA），以输出运算结果。 算术单元可以根据指令作为加法器或乘法器进行操作，从而可以增加整个硬件的使用程度。

公开(公告)号：US20110153878A1

公开(公告)日：2011-06-23

申请号：US12882141

申请日：2010-09-14

申请人： Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

发明人： Ik Jae CHUN ,  Chun Gi Lyuh ,  Se Wan Heo ,  Sang Hun Yoon ,  Tae Moon Roh ,  Jong Kee Kwon ,  Jong Dae Kim

IPC分类号： G06F13/28

CPC分类号： G06F13/28

摘要： Provided are a memory system and an integrated management method for a plurality of direct memory access (DMA) channels. The memory system includes a memory controller exchanging data with a memory and having a plurality of channels physically separated from each other, and a DMA controller having a plurality of DMA channels physically separated from each other and in contact with the plurality of channels of the memory controller, and exchanging data with the memory via the plurality of DMA channels and the memory controller.

摘要翻译： 提供了用于多个直接存储器访问（DMA）通道的存储器系统和集成管理方法。 存储器系统包括存储器控制器，其与存储器交换数据并且具有物理上彼此分离的多个通道;以及DMA控制器，其具有彼此物理上彼此分离并与存储器的多个通道接触的多个DMA通道 控制器，并且经由多个DMA通道和存储器控制器与存储器交换数据。