公开(公告)号：US20110148954A1

公开(公告)日：2011-06-23

申请号：US12963069

申请日：2010-12-08

Applicant: Youichi Tobita ,  Yoshifumi Doi ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Yoshifumi Doi ,  Hiroyuki Murai

IPC: G09G5/02

CPC classification number: G09G3/3688 ,  G09G2310/0281 ,  G09G2310/08

Abstract: For an image display apparatus, cost reduction is enabled to prevent display errors while ensuring operational margin to prevent display errors even when the delay time of gate line driving signals is large. A source driver of a liquid-crystal display apparatus includes a data latch circuit for supplying display data to a decode circuit. A gate line inactivation transition detecting circuit detects inactivation of each of a plurality of gate lines and activates a detect signal for a certain period with that timing. The data latch circuit updates the held display data in response to activation of the detect signal.

Abstract translation: 对于图像显示装置，即使当栅极线驱动信号的延迟时间较大时，也可以降低成本，同时确保操作余量以防止显示错误。 液晶显示装置的源极驱动器包括用于向解码电路提供显示数据的数据锁存电路。 栅极线灭活转变检测电路检测多条栅极线中的每一条的失活，并在该定时激活一段时间的检测信号。 响应于检测信号的激活，数据锁存电路更新保持的显示数据。

公开(公告)号：US09147370B2

公开(公告)日：2015-09-29

申请号：US12963069

申请日：2010-12-08

Applicant: Youichi Tobita ,  Yoshifumi Doi ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Yoshifumi Doi ,  Hiroyuki Murai

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G2310/0281 ,  G09G2310/08

Abstract: For an image display apparatus, cost reduction is enabled to prevent display errors while ensuring operational margin to prevent display errors even when the delay time of gate line driving signals is large. A source driver of a liquid-crystal display apparatus includes a data latch circuit for supplying display data to a decode circuit. A gate line inactivation transition detecting circuit detects inactivation of each of a plurality of gate lines and activates a detect signal for a certain period with that timing. The data latch circuit updates the held display data in response to activation of the detect signal.

Abstract translation: 对于图像显示装置，即使当栅极线驱动信号的延迟时间较大时，也可以降低成本，同时确保操作余量以防止显示错误。 液晶显示装置的源极驱动器包括用于向解码电路提供显示数据的数据锁存电路。 栅极线灭活转变检测电路检测多条栅极线中的每一条的失活，并在该定时激活一段时间的检测信号。 响应于检测信号的激活，数据锁存电路更新保持的显示数据。

公开(公告)号：US07499518B2

公开(公告)日：2009-03-03

申请号：US11532750

申请日：2006-09-18

Applicant: Youichi Tobita ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Hiroyuki Murai

IPC: G11C19/00

CPC classification number: G11C19/184 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/027 ,  G11C19/28

Abstract: A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.

Abstract translation: 移位寄存器包括在输出级中连接在输出端和第一时钟端之间的第一晶体管和连接在输出端和第一电源端之间的第二晶体管。 第三和第四晶体管构成反相器，其反转第二晶体管的栅极的电平并将其输出到第一晶体管的栅极。 由第五晶体管和第六晶体管形成的隔离电路设置在第一晶体管的栅极和第四晶体管的栅极之间。 第五个晶体管是二极管连接的。 当第一晶体管的栅极变得高于第四晶体管的栅极时，第一和第四晶体管彼此电隔离。

公开(公告)号：US07289593B2

公开(公告)日：2007-10-30

申请号：US11258058

申请日：2005-10-26

Applicant: Youichi Tobita ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Hiroyuki Murai

IPC: G11C19/00

CPC classification number: G11C19/28 ,  G09G3/3677 ,  G11C19/184

Abstract: A shift register has an output stage formed by a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a ground. Third and fourth transistors are connected in series between the gate of the first transistor (first node) and the ground. A second node between the third and fourth transistors is connected to a power source via a fifth transistor. The fifth transistor has its gate connected to the first node. Accordingly, when the third and fourth transistors are turned off to raise the first node in level, the fifth transistor is turned on, whereby a predetermined voltage is applied to the second node.

Abstract translation: 移位寄存器具有由连接在输出端子和第一时钟端子之间的第一晶体管和连接在输出端子与地之间的第二晶体管形成的输出级。 第三和第四晶体管串联连接在第一晶体管（第一节点）的栅极和地之间。 第三和第四晶体管之间的第二节点经由第五晶体管连接到电源。 第五晶体管的栅极连接到第一节点。 因此，当第三和第四晶体管关断以使第一节点升高时，第五晶体管导通，由此向第二节点施加预定电压。

公开(公告)号：US07443944B2

公开(公告)日：2008-10-28

申请号：US11838416

申请日：2007-08-14

Applicant: Youichi Tobita ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Hiroyuki Murai

IPC: G11C19/00

CPC classification number: G11C19/28

Abstract: A unit shift register includes a first transistor for supplying an output terminal with a clock signal, and second and third transistors for discharging the output terminal, and further includes a fourth transistor having its gate connected to the gate node of the second transistor and discharging the gate node of the first transistor, and a fifth transistor having its gate connected to the gate node of the third transistor and discharging the gate node of the first transistor. Input of the clock signal is prohibited just after the change in level of first and second control signals for switching between the second and third transistors.

Abstract translation: 单元移位寄存器包括用于向输出端子提供时钟信号的第一晶体管，以及用于对输出端子进行放电的第二和第三晶体管，并且还包括其栅极连接到第二晶体管的栅极节点的第四晶体管， 栅极节点和第五晶体管，其栅极连接到第三晶体管的栅极节点并且对第一晶体管的栅极节点放电。 在第二和第三晶体管之间切换的第一和第二控制信号的电平改变之后，禁止时钟信号的输入。

公开(公告)号：US20070147573A1

公开(公告)日：2007-06-28

申请号：US11532750

申请日：2006-09-18

Applicant: Youichi Tobita ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Hiroyuki Murai

IPC: G11C19/00

CPC classification number: G11C19/184 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/027 ,  G11C19/28

Abstract: A shift register includes, in the output stage, a first transistor connected between an output terminal and a first clock terminal and a second transistor connected between the output terminal and a first power terminal. Third and fourth transistors constitute an inverter which inverses the level of the gate of the second transistor and outputs it to the gate of the first transistor. An isolation circuit formed by fifth and sixth transistors is provided between the gate of the first transistor and the gate of the fourth transistor. The fifth transistor is diode-connected. When the gate of the first transistor becomes higher than the gate of the fourth transistor, the first and fourth transistors are electrically isolated from each other.

Abstract translation: 移位寄存器包括在输出级中连接在输出端和第一时钟端之间的第一晶体管和连接在输出端和第一电源端之间的第二晶体管。 第三和第四晶体管构成反相器，其反转第二晶体管的栅极的电平并将其输出到第一晶体管的栅极。 由第五晶体管和第六晶体管形成的隔离电路设置在第一晶体管的栅极和第四晶体管的栅极之间。 第五个晶体管是二极管连接的。 当第一晶体管的栅极变得高于第四晶体管的栅极时，第一和第四晶体管彼此电隔离。

公开(公告)号：US20060208775A1

公开(公告)日：2006-09-21

申请号：US11265076

申请日：2005-11-03

Applicant: Youichi Tobita ,  Seiichirou Mori ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Seiichirou Mori ,  Hiroyuki Murai

IPC: H03B19/00

CPC classification number: H02M3/07 ,  G09G3/3696 ,  G09G2330/028 ,  H03B19/14

Abstract: A level shifter and a charge pump circuit are added, among cascade-connected unit frequency dividing circuits forming a frequency dividing circuit, to the unit frequency dividing circuit in the first stage. The charge pump circuit boosts an input voltage based on a dot clock signal, and supplies the booster voltage to the unit frequency dividing circuit in the first stage. The unit frequency dividing circuit in the first stage, which is driven by the booster voltage, attains an improved current driving capability. The improved current driving capability of the unit frequency dividing circuit in the first stage to which the dot clock signal of high frequency is input leads to a widened operating margin of the frequency dividing circuit.

公开(公告)号：US07504869B2

公开(公告)日：2009-03-17

申请号：US11265076

申请日：2005-11-03

Applicant: Youichi Tobita ,  Seiichirou Mori ,  Hiroyuki Murai

Inventor： Youichi Tobita ,  Seiichirou Mori ,  Hiroyuki Murai

IPC: H03K21/00

CPC classification number: H02M3/07 ,  G09G3/3696 ,  G09G2330/028 ,  H03B19/14

Abstract: A level shifter and a charge pump circuit are added, among cascade-connected unit frequency dividing circuits forming a frequency dividing circuit, to the unit frequency dividing circuit in the first stage. The charge pump circuit boosts an input voltage based on a dot clock signal, and supplies the booster voltage to the unit frequency dividing circuit in the first stage. The unit frequency dividing circuit in the first stage, which is driven by the booster voltage, attains an improved current driving capability. The improved current driving capability of the unit frequency dividing circuit in the first stage to which the dot clock signal of high frequency is input leads to a widened operating margin of the frequency dividing circuit.

Abstract translation: 在形成分频电路的级联连接单元分频电路中，将电平移位器和电荷泵电路加到第一级中的单位分频电路。 电荷泵电路基于点时钟信号来提高输入电压，并将升压电压提供给第一级中的单位分频电路。 由升压电压驱动的第一级中的单位分频电路获得改善的电流驱动能力。 在输入高频点时钟信号的第一级中的单位分频电路的改进的电流驱动能力导致分频电路加宽的工作裕度。

公开(公告)号：US20080187089A1

公开(公告)日：2008-08-07

申请号：US11968470

申请日：2008-01-02

Applicant: Takashi Miyayama ,  Youichi Tobita ,  Hiroyuki Murai ,  Seiichiro Mori

Inventor： Takashi Miyayama ,  Youichi Tobita ,  Hiroyuki Murai ,  Seiichiro Mori

IPC: G11C19/00 ,  H03L5/00

CPC classification number: G11C19/28

Abstract: A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.

Abstract translation: 由串联在第一电源端子和第一节点之间的两个晶体管形成的双栅极晶体管用作充电电路，用于对旨在上拉单元偏移的输出端子的晶体管的栅极节点（第一节点）充电 寄存器。 双栅极晶体管被配置为使得构成双栅极晶体管的两个晶体管之间的连接节点（第二节点）根据栅极和第二节点的变化被下拉到L电平 门从H级到L级。

公开(公告)号：US08023610B2

公开(公告)日：2011-09-20

申请号：US11968470

申请日：2008-01-02

Applicant: Takashi Miyayama ,  Youichi Tobita ,  Hiroyuki Murai ,  Seiichiro Mori

Inventor： Takashi Miyayama ,  Youichi Tobita ,  Hiroyuki Murai ,  Seiichiro Mori

IPC: G11C19/00

CPC classification number: G11C19/28

Abstract: A dual-gate transistor formed of two transistors connected in series between a first power terminal and a first node is used as a charging circuit for charging a gate node (first node) of a transistor intended to pull up an output terminal of a unit shift register. The dual-gate transistor is configured such that the connection node (second node) between the two transistors constituting the dual-gate transistor is pulled down to the L level by the capacitive coupling between the gate and second node in accordance with the change of the gate from the H level to the L level.