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公开(公告)号：US07599979B2
公开(公告)日：2009-10-06
申请号：US11046340
申请日：2005-01-28
申请人： Yong Je Choi , Ku Young Chang , Do Won Hong , Hyun Sook Cho
发明人： Yong Je Choi , Ku Young Chang , Do Won Hong , Hyun Sook Cho
IPC分类号： G06F7/72
CPC分类号： G06F7/724
摘要： An apparatus and method for hybrid multiplication in GF(2m) by which trade-off between the area and the operation speed of an apparatus for a hybrid multiplier in finite field GF(2m) can be achieved are provided. The apparatus for hybrid multiplication includes: a matrix Z generation unit generating [m×k] matrix Z for performing a partial multiplication of a(x) and b(x), by dividing b(x) by k bits (k≦┌m/2┐), when multiplication of m-bit multiplier a(x) and m-bit multiplicand b(x) is performed from [(m+k−1)×k] coefficient matrix of a(x) in GF(2m); a partial multiplication unit performing the partial multiplication ┌m/k┐k−1 times in units of rows of the matrix Z to calculate an (┌m/k┐k−1)-th partial multiplication value and a final result value of the multiplication; and a reduction unit receiving the (┌m/k┐k−1)-th partial multiplication value fed back from the partial multiplication unit and performing reduction of the value in order to obtain a partial multiplication value next to the (┌m/k┐k−1)-th partial multiplication value.
摘要翻译： 提供了一种用于在GF（2m）中的混合乘法的装置和方法，通过该方法可以实现有限域GF（2m）中用于混合乘法器的装置的区域和操作速度之间的权衡。 用于混合乘法的装置包括：通过将b（x）除以k位（k <=┌m/ m）来生成用于执行a（x）和b（x）的部分相乘的[mxk]矩阵Z的矩阵Z生成单元 在GF（2m）中的（x）的[（m + k-1）×k]系数矩阵中执行m比特乘法器a（x）和m比特被乘数b（x）的乘法时， 部分乘法单元以矩阵Z的行为单位执行部分乘法┌m/k┐k-1次，以计算（┌m/k┐k-1）个部分乘法值和最终结果值 乘法; 以及缩小单元，接收从部分乘法单元反馈的（┌m/k┐k-1）个部分相乘值，并执行该值的减少，以获得与（┌m/ k ┐k-1）部分乘法值。
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公开(公告)号：US07197141B2
公开(公告)日：2007-03-27
申请号：US10318034
申请日：2002-12-13
申请人： Moo Seop Kim , Ho Won Kim , Yong Je Choi , Young Soo Park , Kyo Il Chung , Heui Su Ryu
发明人： Moo Seop Kim , Ho Won Kim , Yong Je Choi , Young Soo Park , Kyo Il Chung , Heui Su Ryu
摘要： Disclosed is an RSA cryptographic processing apparatus capable of performing the fast operating function. A modular multiplication operation or a modular exponentiation operation, i.e., an RSA cryptographic operation, is selectively performed according to a control signal inputted, the modular operation of the data of 512 to 1024 bits is iteratively performed by use of 32-bit operating unit, and the data of 512 to 1024 bits is operated by use of a 32-bit operating unit, thereby minimizing the size of the register storing the data and reducing the size of the cryptographic apparatus, and which the intermediate value generated at the operation process is stored in the internal register instead of the memory, thereby minimizing the times of access to the memory.
摘要翻译： 公开了能够执行快速操作功能的RSA密码处理装置。 根据输入的控制信号有选择地执行模乘法运算或模幂运算，即RSA密码运算，通过使用32位运算单元迭代地执行512比1024位数据的模数运算， 并且通过使用32位操作单元来操作512到1024位的数据，从而最小化存储数据的寄存器的大小并减小密码装置的大小，以及在操作过程中产生的中间值是 存储在内部寄存器中，而不是存储器，从而最小化对存储器的访问次数。
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公开(公告)号：US20120093308A1
公开(公告)日：2012-04-19
申请号：US13016015
申请日：2011-01-28
申请人： Yong Je Choi
发明人： Yong Je Choi
CPC分类号： H03K19/20 , H04L9/003 , H04L9/0866 , H04L2209/046
摘要： Provided are an apparatus and method for generating random data to be used when masking data to be ciphered. The apparatus for generating random data according to an exemplary embodiment of the present invention is an apparatus for generating a random function using a physically unclonable function (PUF) logic. The apparatus for generating random data logically operates first data and second data using two different types of logic gates, and inverts the logical operation values selected from the logically operated first data and second data every odd sequence and then, inputs them as the second data again, thereby making it possible to form the output data as the random data. The present invention is applied to a data encryption apparatus for encrypting data to prevent a side channel attack.
摘要翻译： 提供一种用于在屏蔽要加密的数据时产生要使用的随机数据的装置和方法。 根据本发明的示例性实施例的用于产生随机数据的装置是使用物理不可克隆功能（PUF）逻辑产生随机函数的装置。 用于产生随机数据的装置使用两种不同类型的逻辑门逻辑地操作第一数据和第二数据，并且将每个奇数序列中从逻辑操作的第一数据和第二数据中选择的逻辑运算值反转，然后再将它们作为第二数据输入 ，从而可以形成输出数据作为随机数据。 本发明应用于数据加密装置，用于加密数据以防止侧信道攻击。
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