公开(公告)号：US12248761B2

公开(公告)日：2025-03-11

申请号：US18129762

申请日：2023-03-31

Applicant: XILINX, INC.

Inventor： Riyas Noorudeen Remla ,  Warren E. Cory

IPC: G06F5/06 ,  G06F1/10

Abstract: Embodiments herein describe a solution for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths. Proposed approaches look for a stable region between read and write clock phases by sweeping one of the clock phases until the leading edges (phases) of both clocks are aligned then releasing the write and read resets deterministically based upon a change in cyclic behavior of detected logic levels of a reset beacon waveform.

公开(公告)号：US10038450B1

公开(公告)日：2018-07-31

申请号：US14965752

申请日：2015-12-10

Applicant: Xilinx, Inc.

Inventor： Warren E. Cory

IPC: H03L7/00 ,  H03M9/00

CPC classification number: H03L7/00 ,  G06F5/06 ,  H03K5/135 ,  H03M9/00

Abstract: A circuit for transmitting data in an integrated circuit device is described. The circuit comprises a first data width conversion circuit configured to receive a first portion of transmit data to be transmitted in parallel; a first parallel-in, serial-out circuit configured to receive an output of the first data width conversion circuit; a first reset timer configured to provide a first reset signal to enable resetting the first data width conversion circuit; a second data width conversion circuit configured to receive a second portion of the transmit data; a second parallel-in, serial-out circuit configured to receive an output of the second data width conversion circuit; and a second reset timer configured to provide a second reset signal to enable resetting the second data width conversion circuit.

公开(公告)号：US10033523B1

公开(公告)日：2018-07-24

申请号：US15676667

申请日：2017-08-14

Applicant: Xilinx, Inc.

Inventor： Riyas Noorudeen Remla ,  Warren E. Cory

IPC: H04L7/00 ,  H04L7/04

Abstract: A circuit for measuring latency in an integrated circuit device is described. The circuit comprises a transmitter circuit having signal generator configured to generate a test signal having a marker for determining a latency in a path associated with the integrated circuit device; and a latency calculation circuit coupled to the signal generator and having a latency adjustment circuit and a unit interval (UI) adjustment circuit; wherein the latency calculation circuit generates a latency value (LATENCY) based upon a latency count from the latency adjustment circuit and a UI adjustment from the UI adjustment circuit.

公开(公告)号：US10528513B1

公开(公告)日：2020-01-07

申请号：US15967473

申请日：2018-04-30

Applicant: Xilinx, Inc.

Inventor： Chee Chong Chan ,  Warren E. Cory ,  Jason R. Bergendahl

IPC: G06F1/3296 ,  G06F13/40 ,  H03K19/0175 ,  G06F1/10 ,  G01R31/317 ,  G06F17/50

Abstract: An integrated circuit comprises programmable resources; a plurality of hard blocks; and a programmable connector coupled to the programmable resources, the plurality of hard blocks; wherein the programmable connector is configurable to route signals between a first hard block and a second hard block in a first mode of operation and to route signals between the first hard and the programmable resources in a second mode of operation.