公开(公告)号：US12160256B2

公开(公告)日：2024-12-03

申请号：US17559592

申请日：2021-12-22

Applicant: XILINX, INC.

Inventor： Chi Fung Poon ,  Chuen-Huei Chou ,  Weerachai Neeranartvong ,  Kevin Zheng

IPC: H04B1/04 ,  H03M1/66 ,  H03M1/74

Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

公开(公告)号：US10998307B1

公开(公告)日：2021-05-04

申请号：US16889533

申请日：2020-06-01

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Chuen-Huei Chou ,  Hsung Jai Im

IPC: H03M1/00 ,  H01L27/02 ,  H01L27/092 ,  H03M1/66 ,  H03G3/00

Abstract: An analog signal buffer is disclosed. The analog signal buffer may include a transconductance cell and an active load. The active load may load the current from the transconductance cell with a PMOS transistor and an NMOS transistor and provide a feedback resistance. A transimpedance amplifier is disclosed. The transimpedance amplifier may include a first cell configured to receive a first signal and output a second signal and a second cell coupled to the first cell. The second cell may include an active feedback structure configured to couple an output of the second cell to an input of the second cell.

公开(公告)号：US11177984B1

公开(公告)日：2021-11-16

申请号：US16889573

申请日：2020-06-01

Applicant: Xilinx, Inc.

Inventor： Kevin Zheng ,  Chuen-Huei Chou ,  Hsung Jai Im

IPC: H03H7/40 ,  H04L25/03 ,  H04L27/01 ,  H01L21/8238

Abstract: A continuous time linear equalizer (CTLE) is disclosed. The CTLE may include a first cell configured to buffer and invert an input signal and generate a first intermediate signal, a second cell configured to buffer and invert the input signal and generate a second intermediate signal, and a first frequency section configured to selectively buffer and invert a first range of frequencies of the second intermediate signal. The first frequency section may include a first tunable resistor configured to provide a first resistance and a third cell coupled to the first tunable resistor configured to generate a third intermediate signal based on the first resistance.

公开(公告)号：US12126335B2

公开(公告)日：2024-10-22

申请号：US18115588

申请日：2023-02-28

Applicant: XILINX, INC.

Inventor： Li-Yang Chen ,  Chi Fung Poon ,  Chuen-Huei Chou

IPC: H04B1/04 ,  H03K17/00 ,  H03K17/693 ,  H04B1/40

CPC classification number: H03K17/693 ,  H03K17/005 ,  H04B1/0483 ,  H04B1/40

Abstract: A transmission system is disclosed including a driver circuit. The driver circuit includes multiplexer circuits that receive parallel data and operate as a differential pair. At least one of the multiplexer circuits is coupled to a first circuit node and a second circuit node of the driver circuit. The at least one the multiplexer circuits outputs serial data from the multiplexer circuits at the first and second circuit nodes. The first and second nodes are coupled to a differential output network. The first and second nodes are coupled to an inductor circuit. The first and second nodes are coupled to a cross-coupled circuit. The inductor circuit drains driver circuit current at the first circuit node. The second circuit node and the cross-coupled circuit steer driver circuit current at the first circuit node and the second circuit node.