公开(公告)号：US20250104904A1

公开(公告)日：2025-03-27

申请号：US18373916

申请日：2023-09-27

Applicant: XILINX, INC.

Inventor： Jing JING ,  Shuxian WU

IPC: H01F27/28

Abstract: Examples herein describe inductor circuitry including an inductor coil having a helical shape. The inductor coil includes a first turn and a second turn which are disposed within an isolation wall. The isolation wall extends above the inductor coil and below the inductor coil. The inductor circuitry includes an inductor leg which extends through an aperture of the isolation wall. The inductor leg includes a first portion which is disposed within the isolation wall and a second portion that is disposed outside of the isolation wall.

公开(公告)号：US20230268306A1

公开(公告)日：2023-08-24

申请号：US17680223

申请日：2022-02-24

Applicant: XILINX, INC.

Inventor： Jing JING ,  Shuxian WU

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L24/24 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/20 ,  H01L2924/3025 ,  H01L2924/19042 ,  H01L2924/19011 ,  H01L2224/24226 ,  H01L2224/2401 ,  H01L2224/244 ,  H01L2224/2101 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/2105 ,  H01L2224/2405

Abstract: A chip package and method for fabricating the same are provided that includes an off-die inductor. The off-die inductor is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The redistribution layer is connected to a package substrate to form the chip package.

公开(公告)号：US20210159212A1

公开(公告)日：2021-05-27

申请号：US16694476

申请日：2019-11-25

Applicant: XILINX, INC.

Inventor： Jing JING ,  Shuxian WU ,  Xin X. WU ,  Yohan FRANS

IPC: H01L25/065 ,  H01L23/64 ,  H01L23/522 ,  H01L23/538 ,  H01L49/02 ,  H01L21/48 ,  H01L25/00

Abstract: Examples described herein provide for an isolation design for an inductor of a stacked integrated circuit device. An example is a multi-chip device comprising a chip stack comprising: a plurality of chips, neighboring pairs of the plurality of chips being bonded together, each chip comprising a semiconductor substrate, and a front side dielectric layer on a front side of the semiconductor substrate; an inductor disposed in a backside dielectric layer of a first chip of the plurality of chips, the backside dielectric layer being on a backside of the semiconductor substrate of the first chip opposite from the front side of the semiconductor substrate of the first chip; and an isolation wall extending from the backside dielectric layer of the first chip to the front side dielectric layer, the isolation wall comprising a through substrate via of the first chip, the isolation wall being disposed around the inductor.

公开(公告)号：US20240071958A1

公开(公告)日：2024-02-29

申请号：US17896972

申请日：2022-08-26

Applicant: XILINX, INC.

Inventor： Hong SHI ,  Li-Sheng WENG ,  Frank Peter LAMBRECHT ,  Jing JING ,  Shuxian WU

IPC: H01L23/64 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/645 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/16 ,  H01L24/24 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/24225 ,  H01L2224/73209 ,  H01L2924/1427 ,  H01L2924/30107

Abstract: A chip package and method for fabricating the same are provided that includes embedded off-die inductors coupled in series. One of the off-die inductors is disposed in a redistribution layer formed on a bottom surface of an integrated circuit (IC) die. The other of the series connected off-die inductors is disposed in a substrate of the chip package. The substrate may be either an interposer or a package substrate.