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公开(公告)号:US20170235171A1
公开(公告)日:2017-08-17
申请号:US14907556
申请日:2015-12-31
Inventor: Yue MA
IPC: G02F1/1368 , G02F1/1362 , G02F1/1333 , G02F1/1335
CPC classification number: G02F1/1368 , G02F1/133345 , G02F1/133514 , G02F1/136286 , G02F2001/133357 , G02F2201/07 , G02F2201/121 , G02F2201/123 , G02F2202/10 , H01L27/124 , H01L27/1248
Abstract: The present invention provides an array substrate, and the array substrate includes a substrate, a buffer layer, a semiconductor layer, a gate isolation layer, a gate metal layer, a source drain metal layer, a flat layer, an interlayer insulation layer, a common electrode layer, a passivation layer and a pixel electrode layer, which are sequentially formed on the substrate, wherein the array substrate further comprises a common signal adjustment structure formed at the common electrode layer, and the common signal adjustment structure and the common electrode layer are together employed to be a common electrode for transmitting a common signal to reduce a resistance in a common signal transmission process. The present invention further provides the aforesaid array substrate and a manufacture method thereof, a display device.