公开(公告)号：US07916551B2

公开(公告)日：2011-03-29

申请号：US12138707

申请日：2008-06-13

申请人： Wen-Jer Tsai ,  Ta-Hui Wang ,  Chih-Wei Lee

发明人： Wen-Jer Tsai ,  Ta-Hui Wang ,  Chih-Wei Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/10

摘要： A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/D region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.

摘要翻译： 一种对存储器中的第一单元进行编程的方法，其中所述第一单元具有第一S / D区域并与具有与所述第二S / D区域相反的第三S / D区域的第二单元共享第二S / D区域 。 第一单元和第二单元的通道导通，第一电压施加到第一S / D区，第二电压施加到第二S / D区，第三电压施加到第三S / D区 地区。 第二电压在第一电压和第三电压之间，并且第一至第三电压使载流子从第三S / D区流向第一S / D区，并使第一电池的通道中的热载流子注入 进入第一电池的电荷存储层。

公开(公告)号：US20090116294A1

公开(公告)日：2009-05-07

申请号：US12138707

申请日：2008-06-13

申请人： Wen-Jer Tsai ,  Ta-Hui Wang ,  Chih-Wei Lee

发明人： Wen-Jer Tsai ,  Ta-Hui Wang ,  Chih-Wei Lee

IPC分类号： G11C11/34

CPC分类号： G11C16/10

摘要： A method of programming a first cell in a memory, wherein the first cell has a first S/D region and shares a second S/D region with a second cell that has a third S/D region opposite to the second S/D region. The channels of the first and the second cells are turned on, a first voltage is applied to the first S/D region, a second voltage is applied to the second S/D region and a third voltage is applied to the third S/D region. The second voltage is between the first voltage and the third voltage, and the first to third voltages make carriers flow from the third S/D region to the first S/ID region and cause hot carriers in the channel of the first cell to be injected into the charge storage layer of the first cell.

摘要翻译： 一种对存储器中的第一单元进行编程的方法，其中所述第一单元具有第一S / D区域并与具有与所述第二S / D区域相反的第三S / D区域的第二单元共享第二S / D区域 。 第一单元和第二单元的通道导通，第一电压施加到第一S / D区，第二电压施加到第二S / D区，第三电压施加到第三S / D区 地区。 第二电压在第一电压和第三电压之间，第一至第三电压使载流子从第三S / D区流向第一S / ID区，并使第一电池的通道中的热载流子注入 进入第一电池的电荷存储层。

公开(公告)号：US06512710B1

公开(公告)日：2003-01-28

申请号：US10004636

申请日：2001-12-04

申请人： Wen-Jer Tsai ,  Lan Ting Huang ,  Nian-Kai Zous ,  Ta-Hui Wang

发明人： Wen-Jer Tsai ,  Lan Ting Huang ,  Nian-Kai Zous ,  Ta-Hui Wang

IPC分类号： G11C700

CPC分类号： G11C29/50016 ,  G11C8/08 ,  G11C16/04 ,  G11C29/50

摘要： A reliability test method for a non-volatile memory. A relation curve of gate voltage versus read current degradation rate is obtained. The read current degradation rate of an actual gate voltage is estimated. From the relation curve, an accelerated test gate voltage and a test time corresponding to the actual gate voltage are obtained. With the accelerated test gate voltage, the test is continuously performed within the test time. Afterward, a test result of the memory is then obtained and, by the result, it is judged whether the data is valid or not. If the data is right (retained), the memory can be guarantied to have an expected lifetime; if the data is wrong (lost), the memory is judged as fails to pass the lifetime test.

摘要翻译： 用于非易失性存储器的可靠性测试方法。 获得栅极电压与读取电流退化率的关系曲线。 估计实际栅极电压的读取电流劣化率。 从关系曲线可以得到与实际栅极电压对应的加速测试栅极电压和测试时间。 加速测试门电压，测试在测试时间内连续进行。 然后，获得存储器的测试结果，并且通过结果判断数据是否有效。 如果数据正确（保留），则可以保证存储器具有预期的使用寿命; 如果数据错误（丢失），则存储器被判定为无法通过寿命测试。

公开(公告)号：US06563752B2

公开(公告)日：2003-05-13

申请号：US09945289

申请日：2001-08-30

申请人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

发明人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

IPC分类号： G11C700

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50

摘要： A qualification test method for a non-volatile memory includes determining a relation curve between the programming voltage and the lifetime of the memory cell. A programming voltage with respect to the memory array within the expected lifetime is estimated. According to the relation curve, the accelerating test voltage and the test time period corresponding to the programming voltage operated in the expected lifetime are computed out. The test is performed for the test time period under the accelerating test voltage. All the memory cells at the programmed state are tested to see if the original programmed state still remains. If the programmed state remains, the memory array is judged to have the life period. If the programmed state does not remain, the memory array is judged to have no the life period.

摘要翻译： 用于非易失性存储器的资格测试方法包括确定编程电压与存储器单元的寿命之间的关系曲线。 估计在预期寿命期内相对于存储器阵列的编程电压。 根据该关系曲线计算加速试验电压和对应于在预期寿命中运行的编程电压的试验时间。 在加速测试电压下进行测试时间。 测试编程状态下的所有存储单元，以查看原始编程状态是否仍然保留。 如果编程状态保持不变，则判断存储器阵列具有使用寿命。 如果编程状态不存在，则判断存储器阵列没有寿命周期。

公开(公告)号：US06445614B1

公开(公告)日：2002-09-03

申请号：US09930745

申请日：2001-08-14

申请人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

发明人： Wen-Jer Tsai ,  Nian-Kai Zous ,  Ta-Hui Wang

IPC分类号： G11C1606

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C29/50 ,  G11C2029/1202

摘要： An accelerated test for a non-volatile memory. A threshold voltage variation standard for assessment is selected. A set of negative gate bias voltages is applied to the gate terminals of the non-volatile memory to conduct the accelerated testing and obtain a test result. A curve relating lifetime and negative gate bias voltage is derived from the test result. According to the threshold voltage variation standard, the lifetime of the non-volatile memory is found. A word line negative gate bias voltage generator is coupled to a word line driver to apply a set of negative gate bias voltages to the gate terminals of programmed memory cells and conduct an accelerated testing.

摘要翻译： 非易失性存储器的加速测试。 选择用于评估的阈值电压变化标准。 一组负栅极偏置电压施加到非易失性存储器的栅极端子，以进行加速测试并获得测试结果。 从测试结果得出相关寿命和负栅极偏置电压的曲线。 根据阈值电压变化标准，找到非易失性存储器的寿命。 字线负栅极偏置电压发生器耦合到字线驱动器以将一组负栅极偏置电压施加到编程的存储器单元的栅极端子并进行加速测试。

公开(公告)号：US08698222B2

公开(公告)日：2014-04-15

申请号：US13304380

申请日：2011-11-24

申请人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Cheng-Hsien Cheng

发明人： Shih-Guei Yan ,  Wen-Jer Tsai ,  Cheng-Hsien Cheng

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/792

摘要： A memory device is described, including a tunnel dielectric layer over a substrate, a gate over the tunnel dielectric layer, at least one charge storage layer between the gate and the tunnel dielectric layer, two doped regions in the substrate beside the gate, and a word line that is disposed on and electrically connected to the gate and has a thickness greater than that of the gate.

摘要翻译： 描述了存储器件，包括衬底上的隧道介电层，隧道介电层上的栅极，栅极和隧道介电层之间的至少一个电荷存储层，栅极旁边的衬底中的两个掺杂区域，以及 字线，其设置在栅极上并电连接到栅极并且具有大于栅极的厚度的厚度。

公开(公告)号：US08218364B2

公开(公告)日：2012-07-10

申请号：US13159413

申请日：2011-06-13

申请人： Lit-Ho Chong ,  Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

发明人： Lit-Ho Chong ,  Wen-Jer Tsai ,  Tien-Fan Ou ,  Jyun-Siang Huang

IPC分类号： G11C11/34

CPC分类号： G11C5/04 ,  G11C16/0416 ,  G11C16/10 ,  H01L27/11521 ,  H01L27/11568

摘要： An integrated circuit includes a memory array having a plurality of memory cells arranged in rows and columns, each memory cell including two doped regions and a channel region therebetween, each pair of adjacent memory cells sharing a common doped region, each memory cell having a charge storage member over the channel region and a control gate over the charge storage member. A first word line is coupled to the memory cells in the same row, each of the memory cells designated as the Nth memory cell. Each of a plurality of bit lines is designated as the Nth bit line, the Nth bit line coupled to a doped region shared by the Nth memory cell and the (N−1)th memory cell. The integrated circuit also has a plurality of global bit lines, each of which coupled to two of the bit lines via a switch.

摘要翻译： 集成电路包括具有以行和列排列的多个存储单元的存储器阵列，每个存储单元包括两个掺杂区和它们之间的沟道区，每对相邻的存储单元共用公共掺杂区，每个存储单元具有一个电荷 存储部件，以及位于电荷存储部件上的控制栅极。 第一字线耦合到相同行中的存储器单元，每个存储器单元被指定为第N个存储器单元。 多个位线中的每一行被指定为第N位线，第N位线耦合到由第N存储器单元和第（N-1）个存储器单元共享的掺杂区域。 集成电路还具有多个全局位线，每个位线经由开关耦合到两个位线。

公开(公告)号：US20110305088A1

公开(公告)日：2011-12-15

申请号：US12797994

申请日：2010-06-10

申请人： JYUN-SIANG HUANG ,  Wen-Jer Tsai

发明人： JYUN-SIANG HUANG ,  Wen-Jer Tsai

IPC分类号： G11C16/04

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418

摘要： A memory device includes a plurality of memory cells arranged in series in the semiconductor body, such as a NAND string, having a plurality of word lines. A selected memory cell is programmed by hot carrier injection using a boosted channel potential to establish the heating field. Boosted channel hot carrier injection can be based on blocking flow of carriers between a first side of a selected cell and a second side of the selected cell in the NAND string, boosting by capacitive coupling the first semiconductor body region to a boosted voltage level, biasing the second semiconductor body region to a reference voltage level, applying a program potential greater than a hot carrier injection barrier level to the selected cell and enabling flow of carriers from the second semiconductor body region to the selected cell to cause generation of hot carriers.

摘要翻译： 存储器件包括串联布置在半导体本体中的多个存储单元，例如具有多个字线的NAND串。 通过使用升压通道电位的热载流子注入来对选定的存储单元进行编程以建立加热场。 升压通道热载流子注入可以基于阻塞NAND串中选定单元的第一侧和所选单元的第二侧之间的载流子的流动，通过将第一半导体体区域电容耦合到提升的电压电平来提升 将第二半导体主体区域设置为参考电压电平，将大于热载流子注入势垒级的编程电位施加到所选择的单元，并且使载流子能够从第二半导体体区域流向所选择的单元以引起热载流子的产生。

公开(公告)号：US20080164523A1

公开(公告)日：2008-07-10

申请号：US11619663

申请日：2007-01-04

申请人： Ta-Wei Lin ,  Wen-Jer Tsai

发明人： Ta-Wei Lin ,  Wen-Jer Tsai

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/10802 ,  H01L21/84 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

摘要： A dynamic random access memory cell and a manufacturing method thereof are provided. First, a substrate on which a bottom oxide layer and a semiconductor layer are formed is provided. The semiconductor layer is formed on the bottom oxide layer. Next, a gate is formed on the semiconductor layer. Then, the semiconductor layer is patterned to expose a portion of the bottom oxide layer. Afterwards, an insulation layer is formed at the side walls of the semiconductor layer, wherein the height of the insulation layer is shorter than that of the semiconductor layer, so that a gap is formed between the tops of the insulation layer and the semiconductor layer. Further, a doping layer covering the insulation layer and having the same height with the semiconductor layer is formed on the bottom oxide layer. The doping layer contacts the side walls of the semiconductor layer via the gap.

摘要翻译： 提供了一种动态随机存取存储单元及其制造方法。 首先，提供形成有底部氧化物层和半导体层的基板。 半导体层形成在底部氧化物层上。 接下来，在半导体层上形成栅极。 然后，对半导体层进行图案化以暴露底部氧化物层的一部分。 之后，在半导体层的侧壁形成绝缘层，其中绝缘层的高度比半导体层的高度短，从而在绝缘层的顶部和半导体层之间形成间隙。 此外，在底部氧化物层上形成覆盖绝缘层并且与半导体层具有相同高度的掺杂层。 掺杂层经由间隙与半导体层的侧壁接触。

公开(公告)号：USD490430S1

公开(公告)日：2004-05-25

申请号：US29173199

申请日：2002-12-26

申请人： Wen-Jer Tsai

设计人： Wen-Jer Tsai