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公开(公告)号：US20110214127A1
公开(公告)日：2011-09-01
申请号：US13103345
申请日：2011-05-09
Applicant: Wei-Han Lien , Po-Yung Chang
Inventor： Wei-Han Lien , Po-Yung Chang
IPC: G06F9/46
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
Abstract translation: 在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。 退休单元被配置为响应于已经被处理的第一存储存储器操作至少停止针对第一存储器存储器操作报告异常的流水线阶段而退出第一存储存储器操作。 加载/存储单元包括具有分配给第一存储存储器操作的第一条目的队列。 如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。 队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。
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公开(公告)号：US08255670B2
公开(公告)日：2012-08-28
申请号：US12619751
申请日：2009-11-17
Applicant: Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
Inventor： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
CPC classification number: G06F9/3842
Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
Abstract translation: 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。
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3.发明授权Replaying memory operation assigned a load/store buffer entry occupied by store operation processed beyond exception reporting stage and retired from scheduler 有权重新分配内存操作，分配一个加载/存储缓冲区条目，由存储操作占用，处理超出异常报告阶段，并从调度程序中退出公开(公告)号：US07962730B2
公开(公告)日：2011-06-14
申请号：US12323266
申请日：2008-11-25
Applicant: Wei-Han Lien , Po-Yung Chang
Inventor： Wei-Han Lien , Po-Yung Chang
IPC: G06F9/312
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
Abstract translation: 在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。 退休单元被配置为响应于已经被处理的第一存储存储器操作至少停止针对第一存储器存储器操作报告异常的流水线阶段而退出第一存储存储器操作。 加载/存储单元包括具有分配给第一存储存储器操作的第一条目的队列。 如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。 队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。
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公开(公告)号：US20100064120A1
公开(公告)日：2010-03-11
申请号：US12619751
申请日：2009-11-17
Applicant: Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
Inventor： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC: G06F9/30
CPC classification number: G06F9/3842
Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledgement indication is asserted that corresponds to an identified replay case of the subset.
Abstract translation: 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于该子集的所识别的重放大小写的确认指示为止。
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公开(公告)号：US07647518B2
公开(公告)日：2010-01-12
申请号：US11546223
申请日：2006-10-10
Applicant: Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
Inventor： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
CPC classification number: G06F9/3842
Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
Abstract translation: 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。
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Patent Agency Ranking
6.发明授权Early retirement of store operation past exception reporting pipeline stage in strongly ordered processor with load/store queue entry retained until completion 有权提前退休的店铺经营过去的异常报告流水线阶段在强有序的处理器中，加载/存储队列条目保留到完成公开(公告)号：US07472260B2
公开(公告)日：2008-12-30
申请号：US11546074
申请日：2006-10-10
Applicant: Wei-Han Lien , Po-Yung Chang
Inventor： Wei-Han Lien , Po-Yung Chang
IPC: G06F9/312
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
Abstract translation: 在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。 退休单元被配置为响应于已经至少处理到第一存储器存储器操作的异常被报告的流水线阶段的第一存储存储器操作而退出第一存储存储器操作。 加载/存储单元包括具有分配给第一存储存储器操作的第一条目的队列。 如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。 队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。
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公开(公告)号：US20080086622A1
公开(公告)日：2008-04-10
申请号：US11546223
申请日：2006-10-10
Applicant: Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
Inventor： Po-Yung Chang , Wei-Han Lien , Jesse Pan , Ramesh Gunna , Tse-Yu Yeh , James B. Keller
IPC: G06F9/30
CPC classification number: G06F9/3842
Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
Abstract translation: 在一个实施例中，处理器包括被配置为发出要执行的第一指令操作和耦合到调度器的执行核心的调度器。 配置为执行第一指令操作，执行核心包括被配置为响应于检测多个重放情况中的至少一个而使第一指令操作重放的多个重放源。 调度器被配置为禁止在多个重放情况的子集的重放之后发出第一指令操作。 调度器被耦合以接收对应于子集中的多个重播案例中的每一个的确认指示，并且被配置为禁止发出第一指令操作，直到确认对应于所识别的该子集的重放情况为止的确认指示为止。
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8.发明授权Early release of resources by proceeding to retire store operations from exception reporting stage but keeping in load/store queue 有权通过从异常报告阶段进行退休存储操作，但保持加载/存储队列，提前发布资源公开(公告)号：US08219787B2
公开(公告)日：2012-07-10
申请号：US13103345
申请日：2011-05-09
Applicant: Wei-Han Lien , Po-Yung Chang
Inventor： Wei-Han Lien , Po-Yung Chang
IPC: G06F9/38
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
Abstract translation: 在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。 退休单元被配置为响应于已经被处理的第一存储存储器操作至少停止针对第一存储器存储器操作报告异常的流水线阶段而退出第一存储存储器操作。 加载/存储单元包括具有分配给第一存储器操作的第一条目的队列。 如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。 队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。
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公开(公告)号：US20090077560A1
公开(公告)日：2009-03-19
申请号：US12323266
申请日：2008-11-25
Applicant: Wei-Han Lien , Po-Yung Chang
Inventor： Wei-Han Lien , Po-Yung Chang
IPC: G06F9/46
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
Abstract translation: 在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。 退休单元被配置为响应于已经被处理的第一存储存储器操作至少停止针对第一存储器存储器操作报告异常的流水线阶段而退出第一存储存储器操作。 加载/存储单元包括具有分配给第一存储存储器操作的第一条目的队列。 如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。 队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。
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公开(公告)号：US20080086623A1
公开(公告)日：2008-04-10
申请号：US11546074
申请日：2006-10-10
Applicant: Wei-Han Lien , Po-Yung Chang
Inventor： Wei-Han Lien , Po-Yung Chang
IPC: G06F9/30
CPC classification number: G06F9/3836 , G06F9/30043 , G06F9/30174 , G06F9/3824 , G06F9/384 , G06F9/3842 , G06F9/3857 , G06F9/3861
Abstract: In one embodiment, a processor comprises a retire unit and a load/store unit coupled thereto. The retire unit is configured to retire a first store memory operation responsive to the first store memory operation having been processed at least to a pipeline stage at which exceptions are reported for the first store memory operation. The load/store unit comprises a queue having a first entry assigned to the first store memory operation. The load/store unit is configured to retain the first store memory operation in the first entry subsequent to retirement of the first store memory operation if the first store memory operation is not complete. The queue may have multiple entries, and more than one store may be retained in the queue after being retired by the retire unit.
Abstract translation: 在一个实施例中，处理器包括退出单元和耦合到其的加载/存储单元。 退休单元被配置为响应于已经被处理的第一存储存储器操作至少停止针对第一存储器存储器操作报告异常的流水线阶段而退出第一存储存储器操作。 加载/存储单元包括具有分配给第一存储存储器操作的第一条目的队列。 如果第一存储存储器操作未完成，则加载/存储单元被配置为将第一存储存储器操作保留在第一存储存储器操作退出之后的第一条目中。 队列可以具有多个条目，并且在由退出单元退休之后，可以在队列中保留多个商店。
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