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公开(公告)号：US11984092B2
公开(公告)日：2024-05-14
申请号：US17051080
申请日：2020-08-28
Inventor： You Pan
IPC: G09G3/36 , G02F1/1368 , G09G3/3266 , G11C19/28
CPC classification number: G09G3/3677 , G09G3/3266 , G09G2330/06
Abstract: The present application discloses a display panel and a display device. The display panel includes a non-display region and a gate driver on array (GOA) unit region in the non-display region. The GOA unit region includes multi-level GOA units arranged in multiple columns, thereby improving a space limitation problem associated with arranging a plurality of GOA units in a display panel while the display panel achieves high resolution.
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公开(公告)号：US20240014220A1
公开(公告)日：2024-01-11
申请号：US17618468
申请日：2021-11-23
Inventor： You Pan
IPC: H01L27/12 , G02F1/1362 , G02F1/1368
CPC classification number: H01L27/124 , G02F1/136209 , G02F1/1368 , G02F1/136286
Abstract: An array substrate comprises a base substrate, a light-shielding layer disposed on the base substrate, and a plurality of transistors disposed in an array on a side of the light-shielding layer away from the base substrate. The light-shielding layer comprises a plurality of light-shielding portions. Orthographic projections of a source terminal of each of the transistors and a drain terminal of one adjacent transistor in a same row on the base substrate are located on one same light-shielding portion, and orthographic projections of a source terminal and a drain terminal of one same transistor on the base substrate are respectively located on two adjacent light-shielding portions that are spaced apart. A display panel comprises the array substrate.
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公开(公告)号：US20250046223A1
公开(公告)日：2025-02-06
申请号：US17290684
申请日：2021-03-23
Inventor： You Pan
IPC: G09G3/20
Abstract: The present disclosure provides a gate driver on array (GOA) circuit including a plurality of GOA units disposed in N-stage cascade, and an nth-stage GOA unit includes a node control module, a pull-up module, a pull-down module, a pull-down maintaining module, and a stop control module, wherein 1
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Patent Agency Ranking
公开(公告)号：US12002434B2
公开(公告)日：2024-06-04
申请号：US17599639
申请日：2021-08-18
Inventor： You Pan
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2300/0852
Abstract: The present embodiment provides a GOA circuit and a display panel, in which the GOA circuit comprises a forward/backward scanning control module, an output module, a potential regulation module, a node control module, and a voltage stabilizer module. A first node and a third node are not conducted when a second node is at a second potential; the first node and the third node are conducted and have a second potential when the second node is at a third potential, wherein the second potential is opposite to the third potential. Thus, GOA circuit's leakage issue existing in the TP suspension stage can be improved.
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公开(公告)号：US11710436B2
公开(公告)日：2023-07-25
申请号：US16972626
申请日：2020-11-20
Inventor： You Pan
CPC classification number: G09G3/20 , H01L27/124 , G09G2300/0408 , G09G2310/0267 , G09G2310/08 , G09G2330/027
Abstract: The present application provides a GOA circuit and a display panel. In the GOA circuit, one of two GOA units of a same stage in GOA sub circuits at left and right sides of the display panel is deployed only with an all-on module and the other one of the two GOA units is deployed only with an all-off module. In such a way, both the number of the all-on modules and the number of the all-off modules required in the GOA unit are halved, thereby reducing the area occupied by the GOA circuit. It is beneficial for realizing a display panel with a narrow bezel.
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公开(公告)号：US12112685B2
公开(公告)日：2024-10-08
申请号：US17623630
申请日：2021-06-01
Inventor： You Pan
IPC: G09G3/30
CPC classification number: G09G3/30 , G09G2310/0267 , G09G2310/08
Abstract: A Gate Driver on Array (GOA) circuit and a display panel are provided. The GOA circuit includes a plurality of cascaded GOA units. An Nth stage GOA unit includes a pull-up control circuit, a pull-up output circuit and a scan direction control circuit. The scan direction control circuit can be controlled by the clock signal to realize the alternating forward and backward scanning. The output terminal of the scan direction control circuit is connected with the output terminal of the pull-up control circuit, and the output terminal potential of the pull-up control circuit can be alternately changed.
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公开(公告)号：US12243461B1
公开(公告)日：2025-03-04
申请号：US18555196
申请日：2023-08-16
Inventor： You Pan , Qiang Gong
IPC: G09G3/20
Abstract: The present disclosure discloses a display panel and a display device. The compensation module in the display panel is configured to input a first compensation voltage to a subpixel in the blank period of the first frame and a second compensation voltage to the subpixel in the blank period of the second frame. The polarity of the first compensation voltage is the same as the polarity of the first data voltage, and the polarity of the second compensation voltage is the same as the polarity of the second data voltage. The first compensation voltage is not zero, and the second compensation voltage is not zero.
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公开(公告)号：US11694586B2
公开(公告)日：2023-07-04
申请号：US17051095
申请日：2020-08-28
Inventor： You Pan
CPC classification number: G09G3/20 , H01L27/124 , G09G2300/0408 , G09G2300/0426 , G09G2310/0213
Abstract: A display panel and a display device are provided. The display panel and display device include gate driver on array (GOA) units in a first column, GOA units in a second column, and signal input lines. By adjusting a positional relationship between the signal input line and the GOA units in the first column and the GOA unit in the second column, the GOA units in the first column and the GOA units in the second column may share the signal input line, so as to save a set of signal input lines and reduce a width of the frame area.
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