MULTIPLEXED DISPLAY PANEL AND DEVICE AND DRIVING METHOD FOR MULTIPLEXED DISPLAY PANEL

    公开(公告)号:US20240071331A1

    公开(公告)日:2024-02-29

    申请号:US17623328

    申请日:2021-12-20

    CPC classification number: G09G3/3677 G09G3/3688 G09G2310/0297

    Abstract: A multiplexed display panel and device and a driving method for the multiplexed display panel are provided. At the moment when a switching switch is turned on, a potential of a fanout line corresponding to a data line connected to sub-pixels, into which an data signal is input, is adjusted to the same level as a potential of the data line as much as possible, and a potential difference between each fanout line and the corresponding data line is relatively small at the moment when the switching switch is turned on, so that an instantaneous current at this moment is greatly reduced without causing relatively large jump of the potential of the data line, a common electrode and back-plated indium tin oxide (ITO) greatly fluctuate, and then the surface noise generated by the display panel is turned on is greatly reduced.

    GOA CIRCUIT AND DISPLAY PANEL
    2.
    发明申请

    公开(公告)号:US20230134368A1

    公开(公告)日:2023-05-04

    申请号:US16970649

    申请日:2020-06-24

    Inventor: Jian TAO

    Abstract: In a GOA circuit and a display panel provided by embodiments of the present application, a reset module is provided in each level of GOA units, so that each level of the GOA units can output a high potential before an end of a frame, all gates in a display area are turned on, and a charge of all pixels in the display area is discharged; after that, each level of the GOA units outputs a low potential, and all of the gates in the display area are set to the low potential.

    GOA CIRCUIT AND DISPLAY PANEL
    3.
    发明申请

    公开(公告)号:US20220005431A1

    公开(公告)日:2022-01-06

    申请号:US16766748

    申请日:2020-03-17

    Inventor: Jian TAO

    Abstract: The present disclosure discloses a gate driver of array (GOA) circuit, which includes a plurality of stage-cascaded GOA units, wherein an N-th GOA unit includes a scan control circuit, a reverse circuit, a gate signal output circuit, and a potential holding circuit. The reverse circuit is coupled to the scan control circuit. The gate signal output circuit is coupled to an N-th clock signal, the scan control circuit, and the reverse circuit. The potential holding circuit is coupled to the scan control circuit, the reverse circuit, and the gate signal output circuit.

    DISPLAY PANEL AND ELECTRONIC APPARATUS

    公开(公告)号:US20220301467A1

    公开(公告)日:2022-09-22

    申请号:US17057762

    申请日:2020-09-29

    Inventor: Jian TAO

    Abstract: A display panel and an electronic apparatus are provided. The display panel includes a substrate comprising a display section, a binding section, and a fan-out section disposed between the display section and the binding section. By disposing a first detecting module on the binding section, and a second detecting module on a side of the fan-out section adjacent to the display section to test whether the signal wires is normal, waste of back-end materials caused by broken signal wires is prevented, and product yields are increased.

    GOA CIRCUIT AND DISPLAY PANEL THEREOF
    7.
    发明公开

    公开(公告)号:US20230154376A1

    公开(公告)日:2023-05-18

    申请号:US16966032

    申请日:2020-04-22

    Inventor: Jian TAO

    Abstract: A gate driver on array (GOA) circuit and a display panel are provided. The GOA circuit provides a pull-up maintaining module including transistors T11, T12, and T13. In a pre-charge sub-phase t1 and an output sub-phase t2, a node Qb is at a high level to pull down a node P and turn off the transistor T13. A node K changes to the high level under control of the transistor T11. The transistor T12 is turned on, and the node Qb is keeping at the high level. A node Qa is keeping at the high level in the pre-charge sub-phase, and keeping at a bootstrap electrical level in the output sub-phase.

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