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公开(公告)号：US11069632B2
公开(公告)日：2021-07-20
申请号：US16614565
申请日：2019-09-16
Inventor： Chao He
IPC: H01L23/60 , H01L27/12 , H01L23/552
Abstract: The present disclosure provides an array substrate. The array substrate includes a plurality of shielding layers disposed on a glass substrate and arranged at intervals; a dielectric layer spread on the glass substrate and covering the shielding layers, wherein the dielectric layer includes a plurality of dielectric patterns, the dielectric patterns include main dielectric patterns and auxiliary dielectric patterns disposed on at least one side of the main dielectric patterns; and a gate insulating layer disposed on the dielectric layer.
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公开(公告)号：US09935137B2
公开(公告)日：2018-04-03
申请号：US15115692
申请日：2016-05-26
Inventor： Chao He
IPC: H01L27/12 , G02F1/1335 , G02F1/1362
CPC classification number: H01L27/1288 , G02F1/133514 , G02F1/1362 , G02F1/136209 , H01L21/77 , H01L27/1222 , H01L27/1274
Abstract: The present invention provides a manufacture method of a LTPS array substrate. By utilizing one halftone mask, the N type heavy doping, the channel doping of the first polysilicon layer of the NMOS region and the P type heavy doping of the second polysilicon layer of the PMOS region, the three processes which previously require three masks are integrated into one mask process, and two exposure processes are eliminated, which significantly raises the exposure capacity, and meanwhile saves the manufacture cost of two masks to effectively reduce the manufacture cost of the LTPS array substrate, and the manufactured LTPS array substrate possesses great electrical property.
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Patent Agency Ranking
公开(公告)号：US09728403B2
公开(公告)日：2017-08-08
申请号：US14787773
申请日：2015-10-13
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Chao He , Guoqiang Tang , Yuan Guo , Juan Li , Yuxia Chen
CPC classification number: H01L21/0242 , G02F1/1333 , G02F1/1362 , G02F2001/13685 , G09G3/2092 , G09G3/3611 , G09G3/3629 , G09G2300/0417 , G09G2300/0495 , H01L21/02576 , H01L21/77 , H01L27/12
Abstract: The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate according to the present invention forms a gate electrode in the same metal layer with source and drain electrodes and divides a common electrode layer that is conventionally in the form of an entire surface into two portions, of which one serves as a common electrode, while the other portion feeds an input of a gate scan signal thereby eliminating an operation of forming an interlayer insulation layer and thus reducing manufacturing cost of the operation. The array substrate of the present invention comprises a gate electrode that is formed in the same metal layer with source and drain electrodes so that no interlayer insulation layer is present between the gate electrode and the source and drain electrodes, thereby simplifying the structure and reducing the manufacturing cost of the array substrate.
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公开(公告)号：US10957606B2
公开(公告)日：2021-03-23
申请号：US16096871
申请日：2018-04-20
Inventor： Yuxia Chen , Chao He
IPC: H01L21/00 , H01L21/8238 , H01L21/02
Abstract: Disclosed is a manufacturing method of a complementary metal oxide semiconductor transistor, comprising a step of implementing a channel doping to an N-type channel region. The step comprises: preparing a low temperature polysilicon layer on a substrate, and patterning the low temperature polysilicon layer to form the N-type channel region correspondingly above a light shielding pattern; coating a negative photoresist on the substrate, and using the light shielding pattern as a mask to implement exposure to the negative photoresist from a back surface of the substrate to form a negative photoresist mask plate exposing the N-type channel region after development; implementing the channel doping to the N-type channel region with shielding of the negative photoresist mask plate. Further disclosed is a manufacturing method of an array substrate, applied with the aforesaid manufacturing method of the complementary metal oxide semiconductor transistor.
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公开(公告)号：US10157940B2
公开(公告)日：2018-12-18
申请号：US15323978
申请日：2016-06-12
Inventor： Yuxia Chen , Chao He
IPC: H01L27/12 , H01L21/02 , H01L21/027 , H01L21/265 , H01L21/3213 , H01L29/66 , H01L29/786
Abstract: The present invention provides a manufacturing method of LTPS array substrate, wherein the LTPS array substrate contains at least a metal mask layer, a buffer layer, an active layer, a gate insulating layer and a gate layer. The manufacturing method is to form the gate layer by patterning the gate layer using the metal mask layer as a photomask, and a width of the formed gate layer is smaller than a width of the metal mask layer so that a vertical projection of the gate layer falls within the scope of the metal mask layer. In the present invention, the cost of producing a metal mask for the gate electrode is saved by patterning the gate layer using the metal mask layer as a photomask, so that the cost of producing LTPS is saved and the process of production is simplified.
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公开(公告)号：US20180069034A1
公开(公告)日：2018-03-08
申请号：US15115692
申请日：2016-05-26
Inventor： Chao He
IPC: H01L27/12 , G02F1/1362 , G02F1/1335
CPC classification number: H01L27/1288 , G02F1/133514 , G02F1/1362 , G02F1/136209 , H01L21/77 , H01L27/1222 , H01L27/1274
Abstract: The present invention provides a manufacture method of a LTPS array substrate. By utilizing one halftone mask, the N type heavy doping, the channel doping of the first polysilicon layer of the NMOS region and the P type heavy doping of the second polysilicon layer of the PMOS region, the three processes which previously require three masks are integrated into one mask process, and two exposure processes are eliminated, which significantly raises the exposure capacity, and meanwhile saves the manufacture cost of two masks to effectively reduce the manufacture cost of the LTPS array substrate, and the manufactured LTPS array substrate possesses great electrical property.
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公开(公告)号：US20170200600A1
公开(公告)日：2017-07-13
申请号：US14787773
申请日：2015-10-13
Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd. , Wuhan China Star Optoelectronics Technology Co., Ltd.
Inventor： Chao He , Guoqiang Tang , Yuan Guo , Juan Li , Yuxia Chen
CPC classification number: H01L21/0242 , G02F1/1333 , G02F1/1362 , G02F2001/13685 , G09G3/2092 , G09G3/3611 , G09G3/3629 , G09G2300/0417 , G09G2300/0495 , H01L21/02576 , H01L21/77 , H01L27/12
Abstract: The present invention provides an array substrate and a manufacturing method thereof. The manufacturing method of the array substrate according to the present invention forms a gate electrode in the same metal layer with source and drain electrodes and divides a common electrode layer that is conventionally in the form of an entire surface into two portions, of which one serves as a common electrode, while the other portion feeds an input of a gate scan signal thereby eliminating an operation of forming an interlayer insulation layer and thus reducing manufacturing cost of the operation. The array substrate of the present invention comprises a gate electrode that is formed in the same metal layer with source and drain electrodes so that no interlayer insulation layer is present between the gate electrode and the source and drain electrodes, thereby simplifying the structure and reducing the manufacturing cost of the array substrate.
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