公开(公告)号：US20150012711A1

公开(公告)日：2015-01-08

申请号：US13935550

申请日：2013-07-04

Applicant: VAKUL GARG ,  Varun Sethi ,  Bharat Bhushan

Inventor： VAKUL GARG ,  Varun Sethi ,  Bharat Bhushan

IPC: G06F12/08

CPC classification number: G06F12/084

Abstract: A system for operating a shared memory of a multiprocessor system includes a set of processor cores and a corresponding set of core local caches, a set of I/O devices and a corresponding set of I/O device local caches. Read and write operations performed on a core local cache, an I/O device local cache, and the shared memory are governed by a cache coherence protocol (CCP) that ensures that the shared memory is updated atomically.

Abstract translation: 用于操作多处理器系统的共享存储器的系统包括一组处理器核心和相应的一组核心本地高速缓存，一组I / O设备和相应的一组I / O设备本地高速缓存。 在本地高速缓存，I / O设备本地缓存和共享存储器上执行的读写操作由缓存一致性协议（CCP）来管理，该协议确保共享存储器以原子方式更新。

公开(公告)号：US20150301975A1

公开(公告)日：2015-10-22

申请号：US14258046

申请日：2014-04-22

Applicant: Vakul Garg ,  Bharat Bhushan

Inventor： Vakul Garg ,  Bharat Bhushan

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/24

CPC classification number: G06F13/4221 ,  G06F13/24 ,  G06F13/4068 ,  H04L49/9021 ,  H04L63/0485

Abstract: A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.

Abstract translation: 用于管理数据包的系统具有多个核心，数据缓冲器，硬件加​​速器和中断控制器。 中断控制器基于从硬件加速器接收到的第一硬件信号将第一中断信号发送到第一核心。 第一核心创建与第一虚拟队列中的数据缓冲器中的数据分组相对应的缓冲器描述符环的缓冲器描述符（BD）的副本，并向硬件加速器指示数据分组被处理。 如果存在额外的数据分组，则中断控制器将第二中断信号发送到第二核心，其执行与由第一核心执行的步骤相同的步骤。 第一和第二核心分别同时处理与第一和第二虚拟队列中的BD相关联的数据分组。

公开(公告)号：US09606926B2

公开(公告)日：2017-03-28

申请号：US14556143

申请日：2014-11-29

Applicant: Vakul Garg ,  Bharat Bhushan

Inventor： Vakul Garg ,  Bharat Bhushan

IPC: G06F12/00 ,  G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1021 ,  G06F2212/6028

Abstract: A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

公开(公告)号：US20160154737A1

公开(公告)日：2016-06-02

申请号：US14556143

申请日：2014-11-29

Applicant: Vakul Garg ,  Bharat Bhushan

Inventor： Vakul Garg ,  Bharat Bhushan

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/1021 ,  G06F2212/6028

Abstract: A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

Abstract translation: 用于将数据帧从系统存储器预取入高速缓冲存储器的系统包括处理器，队列管理器和预取管理器。 处理器发出与数据帧相关联的解除队列请求。 队列管理器接收去队列请求，识别与数据帧相关联的帧描述符，并生成预取提示信号。 预取管理器接收预取提示信号并产生预取信号，并使缓存存储器能够预取数据帧。 随后，队列管理器对帧描述符进行排队。 处理器接收帧描述符并从高速缓冲存储器读取数据帧。

公开(公告)号：US20160274936A1

公开(公告)日：2016-09-22

申请号：US14660905

申请日：2015-03-17

Applicant: VAKUL GARG ,  Bharat Bhushan ,  Ruchika Gupta

Inventor： VAKUL GARG ,  Bharat Bhushan ,  Ruchika Gupta

IPC: G06F9/48 ,  G06F9/46

CPC classification number: G06F9/4881 ,  G06F9/466 ,  G06F9/52

Abstract: A data processing system includes a host processor, a co-processor, and a memory that includes multiple buffer descriptor (BD) rings. The host processor includes multiple cores that execute multiple threads to process data packets stored in the memory. The host processor generates a notification command based on multiple context switch events that occur in the cores. The notification command indicates a context switch event type and BD ring IDs associated with BD rings to be polled by the co-processor. The BD rings are referred to as active BD rings. The co-processor polls only the active BD rings based on the notification command and processes the data packets associated with the active BD rings.

Abstract translation: 数据处理系统包括主处理器，协处理器和包括多个缓冲器描述符（BD）环的存储器。 主处理器包括执行多个线程以处理存储在存储器中的数据分组的多个核。 主机处理器基于核心中发生的多个上下文切换事件来生成通知命令。 通知命令指示与协处理器轮询的BD环相关联的上下文切换事件类型和BD环ID。 BD环被称为活动BD环。 协处理器仅基于通知命令轮询主动BD环，并处理与活动BD环相关联的数据包。

公开(公告)号：US09396154B2

公开(公告)日：2016-07-19

申请号：US14258046

申请日：2014-04-22

Applicant: Vakul Garg ,  Bharat Bhushan

Inventor： Vakul Garg ,  Bharat Bhushan

IPC: G06F13/24 ,  G06F13/42 ,  G06F13/40 ,  H04L12/883

CPC classification number: G06F13/4221 ,  G06F13/24 ,  G06F13/4068 ,  H04L49/9021 ,  H04L63/0485

Abstract: A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.

Abstract translation: 用于管理数据包的系统具有多个核心，数据缓冲器，硬件加​​速器和中断控制器。 中断控制器基于从硬件加速器接收到的第一硬件信号将第一中断信号发送到第一核心。 第一核心创建与第一虚拟队列中的数据缓冲器中的数据分组相对应的缓冲器描述符环的缓冲器描述符（BD）的副本，并向硬件加速器指示数据分组被处理。 如果存在额外的数据分组，则中断控制器将第二中断信号发送到第二核心，其执行与由第一核心执行的步骤相同的步骤。 第一和第二核心分别同时处理与第一和第二虚拟队列中的BD相关联的数据分组。

公开(公告)号：US09569264B2

公开(公告)日：2017-02-14

申请号：US14660905

申请日：2015-03-17

Applicant: Vakul Garg ,  Bharat Bhushan ,  Ruchika Gupta

Inventor： Vakul Garg ,  Bharat Bhushan ,  Ruchika Gupta

IPC: G06F9/48 ,  G06F9/46 ,  G06F9/52

CPC classification number: G06F9/4881 ,  G06F9/466 ,  G06F9/52

Abstract: A data processing system includes a host processor, a co-processor, and a memory that includes multiple buffer descriptor (BD) rings. The host processor includes multiple cores that execute multiple threads to process data packets stored in the memory. The host processor generates a notification command based on multiple context switch events that occur in the cores. The notification command indicates a context switch event type and BD ring IDs associated with BD rings to be polled by the co-processor. The BD rings are referred to as active BD rings. The co-processor polls only the active BD rings based on the notification command and processes the data packets associated with the active BD rings.

Abstract translation: 数据处理系统包括主处理器，协处理器和包括多个缓冲器描述符（BD）环的存储器。 主处理器包括执行多个线程以处理存储在存储器中的数据分组的多个核。 主机处理器基于核心中发生的多个上下文切换事件来生成通知命令。 通知命令指示与协处理器轮询的BD环相关联的上下文切换事件类型和BD环ID。 BD环被称为活动BD环。 协处理器仅基于通知命令轮询主动BD环，并处理与活动BD环相关联的数据包。

公开(公告)号：US07886238B1

公开(公告)日：2011-02-08

申请号：US11564223

申请日：2006-11-28

Applicant: Harsh Dev Sharma ,  Rajeev Srivastava ,  Srinivas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

Inventor： Harsh Dev Sharma ,  Rajeev Srivastava ,  Srinivas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

IPC: G06F17/50

CPC classification number: G06F17/5068 ,  G06F2217/12 ,  Y02P90/265

Abstract: Systems and methods to optimize a layout based on the yield analysis is disclosed. The method includes generating an integrated circuit layout having two or more layers of wire interconnect to form net segments and having one or more via contact layers to couple net segments in the wire interconnect together. The method further includes performing a yield analysis of the net segments in the integrated circuit layout and displaying the net segments with a visual depiction of the yield analysis using multiple levels of opacity to reflect yield scores of the net segments in the integrated circuit layout.

Abstract translation: 公开了基于产量分析优化布局的系统和方法。 该方法包括生成具有两层或更多层导线互连的集成电路布局，以形成网段，并且具有一个或多个通孔接触层以将导线互连中的网段耦合在一起。 该方法还包括对集成电路布局中的网段执行收益率分析，并使用多个不透明度级别对收益率分析的视觉描绘来显示净段以反映集成电路布局中的网段的收益率。

公开(公告)号：US07600208B1

公开(公告)日：2009-10-06

申请号：US11669872

申请日：2007-01-31

Applicant: Harsh Dev Sharma ,  Rajeev Srivastava ,  Srivinas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

Inventor： Harsh Dev Sharma ,  Rajeev Srivastava ,  Srivinas R. Kommoori ,  Bharat Bhushan ,  Mithunjoy Parui ,  Albert Lee

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F17/5068

Abstract: Disclosed are methods, systems and apparatus for automatically placing decoupling capacitors in an integrated circuit to compensate for voltage drops that might otherwise occur in a power grid. In one embodiment of the invention, the method includes generating one or more regions of the integrated circuit design, with each region having one or more cells, determining an amount of decoupling capacitance required in each region of the integrated circuit design by analyzing each cell in the region, and adding sufficient decoupling capacitor cells to the region to compensate for the potential voltage drop.

Abstract translation: 公开了用于在集成电路中自动放置去耦电容器以补偿电网中可能出现的电压降的方法，系统和装置。 在本发明的一个实施例中，该方法包括生成集成电路设计的一个或多个区域，每个区域具有一个或多个单元，通过分析集成电路设计的每个单元来确定集成电路设计的每个区域中所需的去耦电容量 并且向该区域添加足够的去耦电容器单元以补偿潜在的电压降。

公开(公告)号：US07023220B2

公开(公告)日：2006-04-04

申请号：US10967930

申请日：2004-10-19

Applicant: Jonathan P. Pelz ,  David T. Lee ,  Bharat Bhushan

Inventor： Jonathan P. Pelz ,  David T. Lee ,  Bharat Bhushan

IPC: G01R27/26

CPC classification number: G01Q60/46 ,  G01R27/2605 ,  Y10S977/866

Abstract: A method for measuring nm-scale tip-sample capacitance including (a) measuring a cantilever deflection and a change in probe-sample capacitance relative to a reference level as a function of a probe assembly height; (b) fitting out-of-contact data to a function; (c) subtracting the function from capacitance data to get a residual capacitance as a function of the probe assembly height; and (d) determining the residual capacitance at a z-position where the cantilever deflection is zero.

Abstract translation: 一种用于测量nm尺度尖端样本电容的方法，包括（a）测量悬臂偏转和相对于参考水平的探针样品电容的变化，作为探针组件高度的函数; （b）将不合格数据拟合到一个功能上; （c）从电容数据中减去该功能，以获得作为探头组件高度的函数的残余电容; 和（d）确定悬臂偏转为零的z位置处的残余电容。