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公开(公告)号：US11545998B2
公开(公告)日：2023-01-03
申请号：US17276255
申请日：2019-10-07
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Hassan Harb , Emmanuel Boutillon , Cédric Marchand
Abstract: Embodiments of the invention provide an elementary check node processing unit (300) implemented in a check node processing unit of a non-binary error correcting code decoder, the elementary check node processing unit (300) being linked to a variable node processing unit (305) and being configured to receive a first message and a second message, each message comprising at least two components. The elementary check node processing unit (300) comprises a calculation unit (301) which determines two or more auxiliary components from the components comprised in the first message and from the components comprised in the second message, an auxiliary component comprising an auxiliary reliability metrics. The calculation unit (301) also determines, in association with each of the two or more auxiliary components, decoding performance values. The elementary check node processing unit (300) also comprises a selection unit (303) which selects, among the two or more auxiliary components, the auxiliary component that is associated with the optimal decoding performance values and determines an offset value from the auxiliary reliability metrics comprised in the selected auxiliary component. The elementary check node processing unit (300) then transmits the offset value and a selected set of auxiliary components among the two or more auxiliary components to the variable node processing unit (305).
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公开(公告)号：US11245421B2
公开(公告)日：2022-02-08
申请号：US17255101
申请日：2019-07-04
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Emmanuel Boutillon , Cédric Marchand , Hassan Harb
IPC: H03M13/11
Abstract: A sorting device and method for determining elementary check node components in an elementary check node processor implemented in a non-binary error correcting code decoder by sorting auxiliary components are presented. The auxiliary components are stored in a plurality of FIFO memories, each FIFO memory being assigned a FIFO number index. Each auxiliary component stored in a given FIFO memory comprises an auxiliary symbol, a reliability metrics representing the reliability of the auxiliary symbol, and the FIFO number index assigned to the given FIFO memory. The sorting device is configured to sort the auxiliary components by a plurality of multiplexers arranged sequentially. Each multiplexer is configured to initialize a candidate elementary check node component from the components of a FIFO memory corresponding to the auxiliary component which comprise the most reliable auxiliary symbol and to perform one or more iterations of the illustrated receiving, updating and sorting steps.
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3.发明授权公开(公告)号：US11133827B2
公开(公告)日：2021-09-28
申请号：US16622410
申请日：2018-06-07
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Emmanuel Boutillon , Cédric Marchand
Abstract: Embodiments of the invention provide a check node processing unit configured to determine at least one check node message to decode a signal encoded using a NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units to determine permuted variable node messages by applying permutations to at least three variable node messages generated by variable node processing units; a syndrome calculation unit to determine a set of syndromes comprising binary values from the permuted variable node messages; a decorrelation and permutation unit configured, for each check node message of a given index, to: determine a permuted index by applying the inverse of the one or more permutations; select at least one valid syndrome in the set of syndromes; and determine at least one candidate check node component; and a selection unit to determine at least one check node message from the candidate check node component.
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Patent Agency Ranking
公开(公告)号：US11095308B2
公开(公告)日：2021-08-17
申请号：US16621956
申请日：2018-06-07
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Cédric Marchand , Emmanuel Boutillon
IPC: H03M13/11
Abstract: A check node processing unit configured to determine check node messages to decode a signal encoded using NB-LDPC code, the check node processing unit comprising: a data link to one or more message presorting units configured to determine permuted variable node messages by permuting variable node messages generated by one or more variable node processing units; a syndrome sub-check node configured to determine check node messages from a set of syndromes, the set of syndromes being determined from one or more intermediate messages computed from the permuted variable node messages; a forward-backward sub-check node configured to determine permuted check node messages from the intermediate messages; a switching unit configured to generate check node messages of given index from the check node messages or from the permuted check node messages depending on the giving index.
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公开(公告)号：US10476523B2
公开(公告)日：2019-11-12
申请号：US15723813
申请日：2017-10-03
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Cédric Marchand , Emmanuel Boutillon
Abstract: At least a method and an apparatus are presented for decoding a signal. For example, a decoder is presented for determining an estimate of an encoded signal. The decoder comprises one or more variable node processing units and one or more check node processing units configured to exchange messages, each message comprising one or more components, a component comprising a symbol and a reliability metric associated with the symbol. The at least one check processing unit is further configured to calculate at two or more elementary check node processors a set of syndromes from at least three permuted messages, a syndrome comprising a binary vector; generate at least one check node message from the set of syndromes depending on the binary vector, and send the at least one check node message to a signal estimation unit.
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6.发明授权公开(公告)号：US11476870B2
公开(公告)日：2022-10-18
申请号：US17257191
申请日：2019-07-04
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Emmanuel Boutillon , Cédric Marchand , Hassan Harb
IPC: H03M13/11
Abstract: Embodiments of the invention provide a variable node processing unit for a non-binary error correcting code decoder, the variable node processing unit being configured to receive one check node message and intrinsic reliability metrics, and to generate one variable node message from auxiliary components derived from said one check node message and intrinsic reliability metrics, the intrinsic reliability metrics being derived from a received signal, an auxiliary component comprising an auxiliary symbol and an auxiliary reliability metrics associated with said auxiliary symbol, wherein the variable node processing unit comprises: a sorting and redundancy elimination unit configured to process iteratively the auxiliary components and to determine components of the variable node message by iteratively sorting the auxiliary components according to a given order of the auxiliary reliability metrics and keeping a predefined number of auxiliary components comprising the auxiliary symbols that are the most reliable and all different from one another.
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公开(公告)号：US11290128B2
公开(公告)日：2022-03-29
申请号：US16621830
申请日：2018-06-07
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Cédric Marchand , Emmanuel Boutillon
Abstract: Embodiments of the invention provide a decoder comprising at least one check node processing unit configured to receive at least three variable node messages from one or more variable node processing units and to determine one or more check node messages, wherein the at least one check node processing unit comprises at least two blocks of sub-check nodes, each block of sub-check node being configured to: determine a set of sub-check node syndromes from at least one variable node message among the at least three variable node messages; and determine at least one check node message from at least one syndrome.
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8.发明授权公开(公告)号：US10560120B2
公开(公告)日：2020-02-11
申请号：US15694062
申请日：2017-09-01
Applicant: UNIVERSITE DE BRETAGNE SUD
Inventor： Cédric Marchand , Emmanuel Boutillon
Abstract: At least a method and an apparatus are presented to decode a signal encoded using an error correcting code. For example, a decoder comprising a check node processing unit is presented. The check node processing unit is configured to receive at least three input messages and to generate at least one output message. A syndrome calculator is configured to determine a set of syndromes from the at least three input messages using at least two elementary check node processors. A decorrelation unit is configured to determine, in association with at least an output message, a set of candidate components from the set of syndromes. A selection unit is configured to determine at least an output message by selecting components comprising distinct symbols from the set of candidate components associated with the at least an output message.
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