公开(公告)号：US09324724B1

公开(公告)日：2016-04-26

申请号：US14859358

申请日：2015-09-21

Applicant: UNITED MICROELECTRONICS CORPORATION

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Wang Xiang ,  Yi-Shan Chiu

IPC: H01L21/3205 ,  H01L27/115 ,  H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3105 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/311

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66833

Abstract: The present invention provides a method of fabricating a memory structure, especially forming an oxide on top of a spacer to prevent the spacer from being over-etched, the method comprising the steps of: providing a semiconductor substrate; forming a charge trapping layer, a first conducting layer and a capping layer as a gate stack on the substrate; forming a first gate structure by patterning; a plurality of spacers are patterned and disposed adjacent to the sidewall of said gate stack; depositing a second conducting layer on the substrate to cover the first gate structure and the spacer; selectively etching the second conducting layer to expose the top of the spacer; performing an oxidation process to form an oxide on top of the spacer.

Abstract translation: 本发明提供了一种制造存储结构的方法，特别是在间隔物顶部形成氧化物以防止间隔物被过度蚀刻，该方法包括以下步骤：提供半导体衬底; 在基板上形成电荷俘获层，第一导电层和覆盖层作为栅极堆叠; 通过图案化形成第一栅极结构; 多个间隔物被图案化并邻近所述栅极叠层的侧壁设置; 在所述衬底上沉积第二导电层以覆盖所述第一栅极结构和所述间隔物; 选择性地蚀刻第二导电层以暴露间隔物的顶部; 进行氧化处理以在间隔物的顶部形成氧化物。