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    Computer program product for mismatched shaping of an oversampled converter
    2.
    发明授权
    Computer program product for mismatched shaping of an oversampled converter 失效
    用于过采样转换器不匹配整形的计算机程序产品

    公开(公告)号：US06930626B2

    公开(公告)日：2005-08-16

    申请号：US10893994

    申请日：2004-07-20

    申请人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller ,  Eric Fogleman

    发明人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller ,  Eric Fogleman

    IPC分类号： H03M1/06 ,  H03M1/74 ,  H03M3/00

    CPC分类号： H03M1/067 ,  H03M1/74 ,  H03M1/742 ,  H03M3/464 ,  H03M3/502

    摘要： Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.

    摘要翻译： 用于在多位数模转换器（DAC）中频谱整形失配误差的方法和装置。 在一个实施例中，多位DAC由K个分离的多元件子DAC构成，其中K和每个子DAC中的元件数量优选大于2。 接收的数字输入码被分割成与数字输入码相对应的一组K个子码。 所述K个子代码集合可以具有至少N个不同的子代码顺序中的一个，其指定相对于彼此的K个子代码中的每一个的顺序，其中N≥2。 K个子码的总和等于数字输入码。 使用混洗算法来选择至少N个不同的子代码顺序之一。 然后，根据所选择的子代码顺序输出K个子代码集合中的每个子代码。

    System and method for performing digital-to-analog conversion using a sigma-delta modulator
    3.
    发明授权
    System and method for performing digital-to-analog conversion using a sigma-delta modulator 失效
    使用Σ-Δ调制器执行数模转换的系统和方法

    公开(公告)号：US06816097B2

    公开(公告)日：2004-11-09

    申请号：US10379593

    申请日：2003-03-06

    申请人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller

    发明人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller

    IPC分类号： H03M300

    CPC分类号： H03M3/502 ,  H03M3/504

    摘要： The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

    摘要翻译： 本发明涉及一种包括数字Σ-Δ调制器，抽取滤波器和多位DAC的Σ-Δ数模转换（DAC）。 数字Σ-Δ调制器接收数字输入信号并从其产生量化的数字信号。 抽取滤波器接收量化的数字信号并从其产生抽取的数字信号。 多位DAC接收抽取的数字信号并从其产生模拟输出信号。 模拟输出信号代表数字输入信号。

    Method and apparatus for mismatched shaping of an oversampled converter
    4.
    发明授权
    Method and apparatus for mismatched shaping of an oversampled converter 失效
    过采样转换器失配整形的方法和装置

    公开(公告)号：US06771199B2

    公开(公告)日：2004-08-03

    申请号：US10408446

    申请日：2003-04-08

    申请人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller ,  Eric Fogleman

    发明人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller ,  Eric Fogleman

    IPC分类号： H03M166

    CPC分类号： H03M1/067 ,  H03M1/74 ,  H03M1/742 ,  H03M3/464 ,  H03M3/502

    摘要： Methods and apparatuses for spectrally shaping mismatch errors in a multi-bit digital to analog converter (DAC). In an embodiment, the multi-bit DAC is constructed from K separate multi-element sub-DACs, where K and the number of elements in each sub-DAC are each preferably greater than two. A received digital input code is split into a set of K sub-codes corresponding to the digital input code. The set of K sub-codes can have one of at least N different sub-code orders that specify an order of each of the K sub-codes with respect to one another, where N>2. A sum of the K sub-codes equals the digital input code. One of the at least N different sub-code orders is selected using a shuffling algorithm. Then, each sub-code in the set of K sub-codes is output in accordance with the selected sub-code order.

    摘要翻译： 用于在多位数模转换器（DAC）中频谱整形失配误差的方法和装置。 在一个实施例中，多位DAC由K个分离的多元件子DAC构成，其中K和每个子DAC中的元件数量优选大于2。 接收的数字输入码被分割成与数字输入码相对应的一组K个子码。 所述K个子代码集合可以具有至少N个不同的子代码顺序中的一个，其指定相对于彼此的K个子代码中的每一个的顺序，其中N≥2。 K个子码的总和等于数字输入码。 使用混洗算法来选择至少N个不同的子代码顺序之一。 然后，根据所选择的子代码顺序输出K个子代码集合中的每个子代码。

    Sigma-delta digital-to-analog converter
    6.
    发明授权
    Sigma-delta digital-to-analog converter 有权

    公开(公告)号：US06531973B2

    公开(公告)日：2003-03-11

    申请号：US09949814

    申请日：2001-09-12

    申请人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller

    发明人： Todd L. Brooks ,  David S. P. Ho ,  Kevin L. Miller

    IPC分类号： H03M300

    CPC分类号： H03M3/502 ,  H03M3/504

    摘要： The present invention is directed to a sigma-delta digital to analog converted (DAC) including a digital-sigma delta modulator, a decimation filter, and a multi-bit DAC. The digital sigma-delta modulator receives a digital input signal and produces a quantized digital signal therefrom. The decimation filter receives the quantized digital signal and produces a decimated digital signal therefrom. The multi-bit DAC receives the decimated digital signal and produces an analog output signal therefrom. The analog output signal is representative of the digital input signal.

    Nonlinear mapping in digital-to-analog and analog-to-digital converters
    8.
    发明授权
    Nonlinear mapping in digital-to-analog and analog-to-digital converters 有权
    数模转换器和模数转换器的非线性映射

    公开(公告)号：US08018363B2

    公开(公告)日：2011-09-13

    申请号：US12557352

    申请日：2009-09-10

    申请人： Todd L. Brooks ,  Kevin L. Miller ,  Josephus A. Van Engelen

    发明人： Todd L. Brooks ,  Kevin L. Miller ,  Josephus A. Van Engelen

    IPC分类号： H03M3/00

    CPC分类号： H03M7/3013

    摘要： In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

    摘要翻译： 在高保真数字调制器中，提供映射器以最小化多个数模转换器或模数转换器之间的量化噪声，抖动和串扰。 映射器从量化器接收量化电平，并将量化电平映射到输出序列。 映射器包括定义对应于每个量化级别的多个序列的表。 每个序列包括具有多个值之一的两个或多个符号。 映射器还包括选择多个序列之一作为输出序列的发生器。 第一个输出序列的最后一个符号等于下一个输出序列的第一个符号，依此类推。 发生器通过在接收到的每个量化级别的第一和第二序列之间交替来选择输出序列。 发生器通过在接收到的每个奇数值量化电平具有正和负共模能量的序列之间交替来选择输出序列。