公开(公告)号：US07027528B2

公开(公告)日：2006-04-11

申请号：US10895579

申请日：2004-07-21

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

IPC分类号： H04L27/14

CPC分类号： H04N5/21 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/455 ,  H04N5/46 ,  H04N11/002

摘要： Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fc=fS/4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

摘要翻译： 公开了适用于双模QAM / VSB接收机系统的改进的载波恢复和符号定时系统和方法。 载波和符号定时采集和跟踪环路被相位/频率锁定到在给定频率下在输入VSB频谱中提供的插入导频信号。 输入频谱以基带为中心，并且通过等效滤波器提取导频，该等效滤波器用作具有以导频频率为中心的通带的带通滤波器。 由于给出了导频信号的频率，所以在频域中对于任何采样频率的位置是确定性的。 提供了接收机的采样频率，使得该关系被表示为f / c = f S / S / 4。 当通过锁相环路进行跟踪时，如果采样频率f S S S正确，则导频信号将出现在频谱中的正确位置，并且如果采样 频率f S S太高或太低。

公开(公告)号：US06775334B1

公开(公告)日：2004-08-10

申请号：US09433733

申请日：1999-11-03

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

IPC分类号： H03D100

CPC分类号： H04L27/3827 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

公开(公告)号：US07474695B2

公开(公告)日：2009-01-06

申请号：US10895879

申请日：2004-07-21

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H03D1/00 ,  H04L27/06

CPC分类号： H04L27/3827 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

摘要翻译： 公开了改进的决策反馈均衡器和适用于与双模式QAM / VSB接收机系统相关联的决策定向定时恢复系统和方法。 网格解码器与网格编码的8-VSB调制信号上的判决反馈均衡器电路结合操作。 网格解码器包括基于最大似然序列路径输出最大似然判定以及多个中间决定的4状态回溯存储器电路。 沿序列的任何数量的决定可以作为输入信号提供给定时恢复系统循环，其中沿着根据其通过网格解码器的延迟选择的序列的特定决定。 可变延迟电路耦合到定时恢复系统回路的另一个输入，以确保两个输入信号具有相同的时间戳。 最终决策从网格解码器输出到DF​​E，以提高DFE在低SNR环境下的运行能力。 还产生判决序列估计误差信号并用于驱动均衡器的DFE和FFE部分的抽头更新。

公开(公告)号：US06842495B1

公开(公告)日：2005-01-11

申请号：US09433730

申请日：1999-11-03

申请人： Steven T. Jaffe ,  Tian-Min Liu ,  Loke Kun Tan

发明人： Steven T. Jaffe ,  Tian-Min Liu ,  Loke Kun Tan

IPC分类号： H04B1/68 ,  H04L25/03 ,  H04L27/00 ,  H04L27/02 ,  H04L27/06 ,  H04L27/227 ,  H04L27/34 ,  H04L27/38 ,  H04N5/21 ,  H04N5/44 ,  H04N5/46 ,  H04N11/00 ,  H04L27/22

CPC分类号： H04N21/4382 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

摘要翻译： 公开了一种能够接收和解调根据各种调制格式被调制和发送的电视信号信息内容的电视接收机系统。 特别地，该系统能够适应至少8和16-VSB调制信号的接收和解调，以支持美国HDTV应用以及64和256-QAM调制信号，用于欧洲和潜在的美国CATV实现。 该系统包括适于在增强导频信号上进行操作的载波和定时恢复环路以及决策导向的载波相位恢复环路。 相位检测器对I和Q轨道信号进行操作，或从I轨道的希尔伯特变换产生Q轨。 决策定向循环包含网格解码器，以便对序列估计决策进行操作，以改善差的SNR环境下的可靠性。

公开(公告)号：US06411659B1

公开(公告)日：2002-06-25

申请号：US09692805

申请日：2000-10-20

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

IPC分类号： H04L2714

CPC分类号： H04N5/21 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/455 ,  H04N5/46 ,  H04N11/002

摘要： Improved carrier recovery and symbol timing systems and methods suitable for use in connection with a dual-mode QAM/VSB receiver system is disclosed. Carrier and symbol timing acquisition and tracking loops are phase/frequency locked to an inserted pilot signal provided in an input VSB spectrum at a given frequency. An input spectrum is centered about baseband and the pilot is extracted by an equivalent filter which functions as a bandpass filter having pass bands centered about the pilot frequency. Since the pilot signal's frequency is given, its position in the frequency domain for any sampling frequency, is deterministic. The receiver's sampling frequency is provided such that the relationship is expressed as fC=fS4. When tracked by a phase-lock loop, the pilot signal will appear at the correct location in the spectrum if the sampling frequency fS is correct, and will be shifted in one direction or the other if the sampling frequency fS is too high or too low.

摘要翻译： 公开了适用于双模QAM / VSB接收机系统的改进的载波恢复和符号定时系统和方法。 载波和符号定时采集和跟踪环路被相位/频率锁定到在给定频率下在输入VSB频谱中提供的插入导频信号。 输入频谱以基带为中心，并且通过等效滤波器提取导频，该等效滤波器用作具有以导频频率为中心的通带的带通滤波器。 由于给出了导频信号的频率，所以在频域中对于任何采样频率的位置是确定性的。 提供接收机的采样频率，使得该关系表示为fC = fS4。 当通过锁相环路进行跟踪时，如果采样频率fS正确，则导频信号将出现在频谱中的正确位置，并且如果采样频率fS太高或太低，则导频信号将在一个方向或另一个方向上移位 。

公开(公告)号：US06344871B1

公开(公告)日：2002-02-05

申请号：US09685476

申请日：2000-10-10

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe ,  Robert A. Hawley

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe ,  Robert A. Hawley

IPC分类号： H04N538

CPC分类号： H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum. Filter blocks may be added or subtracted in order to optimize the filter response for any number of interference components for which rejection is desired.

摘要翻译： 公开了一种电子可编程滤波器，其选择性地从频带中去除干扰，噪声或失真分量，而不扰乱频带的任何其它信号。 诸如电视频道频谱的输入频带最初被解调为基带并且被应用于滤波器的输入。 基带频谱在复合混频器中与合成频率信号组合，该频率信号在频域中使频谱偏移特征量，以便在DC周围的区域中定位干扰分量。 一旦移位，DC直流的频率分量被直流消除器电路去除，所得到的频谱与随后的合成频率信号混合，后者将频谱转移回原来的表示和基带。 频率信号由可编程频率合成器开发，用户可以使用定义频谱内的干扰信号的频率位置的智能信号进行编程。 可以添加或减少滤波器块以优化对于期望的抑制的任何数量的干扰分量的滤波器响应。

公开(公告)号：US06219088B1

公开(公告)日：2001-04-17

申请号：US09303783

申请日：1999-04-30

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe ,  Robert A. Hawley

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe ,  Robert A. Hawley

IPC分类号： H04N538

CPC分类号： H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： An electronic, programmable filter is disclosed which selectively removes interference, noise or distortion components from a frequency band without perturbing any of the other signals of the band. An input frequency band such as a television channel spectrum is initially demodulated to baseband and applied to the input of the filter. The baseband spectrum is combined in a complex mixer with a synthesized frequency signal that shifts the spectrum a characteristic amount, in the frequency domain, so as to position an interference component in the region about DC. Once shifted, the frequency components about DC are removed by DC canceler circuit and the resulting spectrum is mixed with a subsequent synthesized frequency signal which shifts the spectrum back to its original representation and baseband. The frequency signals are developed by a programmable frequency synthesizer which a user may program with an intelligence signal that defines the frequency location of an interference signal within the spectrum. Filter blocks may be added or subtracted in order to optimize the filter response for any number of interference components for which rejection is desired.

摘要翻译： 公开了一种电子可编程滤波器，其选择性地从频带中去除干扰，噪声或失真分量，而不扰乱频带的任何其它信号。 诸如电视频道频谱的输入频带最初被解调为基带并且被应用于滤波器的输入。 基带频谱在复合混频器中与合成频率信号组合，该频率信号在频域中将频谱偏移特征量，以便在DC周围的区域中定位干扰分量。 一旦移位，DC直流的频率分量被直流消除器电路去除，所得到的频谱与随后的合成频率信号混合，后者将频谱转移回原来的表示和基带。 频率信号由可编程频率合成器开发，用户可以使用定义频谱内的干扰信号的频率位置的智能信号进行编程。 可以添加或减少滤波器块以优化对于期望的抑制的任何数量的干扰分量的滤波器响应。

公开(公告)号：US08098725B2

公开(公告)日：2012-01-17

申请号：US12330064

申请日：2008-12-08

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L27/3827 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

摘要翻译： 公开了改进的决策反馈均衡器和适用于与双模式QAM / VSB接收机系统相关联的决策定向定时恢复系统和方法。 网格解码器与网格编码的8-VSB调制信号上的判决反馈均衡器电路结合操作。 网格解码器包括基于最大似然序列路径输出最大似然判定以及多个中间决策的4状态追迹存储器电路。 沿序列的任何数量的决定可以作为输入信号提供给定时恢复系统循环，具有沿着通过网格解码器的延迟选择的顺序的特定决定。 可变延迟电路耦合到定时恢复系统回路的另一个输入，以确保两个输入信号具有相同的时间戳。 最终决策从网格解码器输出到DF​​E，以提高DFE在低SNR环境下的运行能力。 还产生判决序列估计误差信号并用于驱动均衡器的DFE和FFE部分的抽头更新。

公开(公告)号：US20090086808A1

公开(公告)日：2009-04-02

申请号：US12330064

申请日：2008-12-08

申请人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

发明人： Tian-Min Liu ,  Loke Kun Tan ,  Steven T. Jaffe

IPC分类号： H04L27/01

CPC分类号： H04L27/3827 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： Improved decision feedback equalizer and decision directed timing recovery systems and methods suitable for use in connection with a dual mode QAM/VSB receiver system are disclosed. A trellis decoder operates in conjunction with a decision feedback equalizer circuit on trellis coded 8-VSB modulated signals. The trellis decoder includes a 4-state traceback memory circuit outputting a maximum likelihood decision as well as a number of intermediate decisions based upon the maximum likelihood sequence path. Any number of decisions, along the sequence, may be provided as an input signal to timing recovery system loops, with the particular decision along the sequence chosen on the basis of its delay through the trellis decoder. Variable delay circuitry is coupled to the other input of the timing recovery system loops in order to ensure that both input signals bear the same timestamp. Final decisions are output from the trellis decoder to a DFE in order to enhance the DFE's ability to operate in low SNR environments. A decision sequence estimation error signal is also generated and used to drive the tap updates of both the DFE and an FFE portion of the equalizer.

摘要翻译： 公开了改进的决策反馈均衡器和适用于与双模式QAM / VSB接收机系统相关联的决策定向定时恢复系统和方法。 网格解码器与网格编码的8-VSB调制信号上的判决反馈均衡器电路结合操作。 网格解码器包括基于最大似然序列路径输出最大似然判定以及多个中间决策的4状态追迹存储器电路。 沿序列的任何数量的决定可以作为输入信号提供给定时恢复系统循环，具有沿着通过网格解码器的延迟选择的顺序的特定决定。 可变延迟电路耦合到定时恢复系统回路的另一个输入，以确保两个输入信号具有相同的时间戳。 最终决策从网格解码器输出到DF​​E，以提高DFE在低SNR环境下的运行能力。 还产生判决序列估计误差信号并用于驱动均衡器的DFE和FFE部分的抽头更新。

公开(公告)号：US07403579B2

公开(公告)日：2008-07-22

申请号：US11031107

申请日：2005-01-07

申请人： Steven T. Jaffe ,  Tian-Min Liu ,  Loke Kun Tan

发明人： Steven T. Jaffe ,  Tian-Min Liu ,  Loke Kun Tan

IPC分类号： H04L27/22

CPC分类号： H04N21/4382 ,  H04B1/68 ,  H04L25/03057 ,  H04L27/02 ,  H04L27/066 ,  H04L27/2273 ,  H04L27/3427 ,  H04L27/3827 ,  H04L2025/03382 ,  H04L2025/0342 ,  H04L2025/0349 ,  H04L2025/03503 ,  H04L2027/0032 ,  H04L2027/0042 ,  H04L2027/0057 ,  H04L2027/0067 ,  H04L2027/0087 ,  H04N5/21 ,  H04N5/211 ,  H04N5/44 ,  H04N5/4401 ,  H04N5/46 ,  H04N11/002

摘要： A television receiver system capable of receiving and demodulating television signal information content that has been modulated and transmitted in accordance with a variety of modulation formats is disclosed. In particular, the system is able to accommodate receipt and demodulation of at least 8 and 16-VSB modulated signals in order to support US HDTV applications, as well as 64 and 256-QAM modulated signals, for European and potential US CATV implementations. The system includes carrier and timing recovery loops adapted to operate on an enhanced pilot signal as well as decision directed carrier phase recovery loops. Phase detectors operate on I and Q rail signals, or generate a Q rail from a Hilbert transform of the I rail. Decision directed loops incorporate a trellis decoder in order to operate on sequence estimated decisions for improved reliability in poor SNR environments.

摘要翻译： 公开了一种能够接收和解调根据各种调制格式被调制和发送的电视信号信息内容的电视接收机系统。 特别地，该系统能够适应至少8和16-VSB调制信号的接收和解调，以支持美国HDTV应用以及64和256-QAM调制信号，用于欧洲和潜在的美国CATV实现。 该系统包括适于在增强导频信号上进行操作的载波和定时恢复环路以及决策导向的载波相位恢复环路。 相位检测器对I和Q轨道信号进行操作，或从I轨道的希尔伯特变换产生Q轨。 决策定向循环包含网格解码器，以便对序列估计决策进行操作，以改善差的SNR环境中的可靠性。