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公开(公告)号：US06570264B2
公开(公告)日：2003-05-27
申请号：US09876056
申请日：2001-06-08
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/904
摘要： The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain—drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. The drain-gate connection layer has an extension section extending in a direction toward the drain-gate connection layer. The drain-gate connection layer 41b has an extension section extending in a direction toward the drain-gate connection layer.
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公开(公告)号：US06507124B2
公开(公告)日：2003-01-14
申请号：US09876068
申请日：2001-06-08
IPC分类号： H01L2711
CPC分类号： H01L27/1104 , G11C11/412 , Y10S257/904
摘要： The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define connection wirings of a flip-flop. A p+ type well contact region is provided for every two of the memory cells arranged in the Y-axis direction.
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3.发明授权Semiconductor memory device having different distances between gate electrode layers 有权在栅电极层之间具有不同距离的半导体存储器件公开(公告)号：US06469356B2
公开(公告)日：2002-10-22
申请号：US09876058
申请日：2001-06-08
IPC分类号： H01L2976
CPC分类号： H01L27/1104 , H01L27/0207 , Y10S257/903
摘要： The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.
摘要翻译： 本发明提供了可以减小存储器单元尺寸并校正光接近效应的SRAM。 第一层中的栅极电极层，第二层中的漏极 - 漏极连接层和第三层中的漏极 - 连接层限定了触发器的导电层。 负载晶体管的源极接触层位于栅极电极层的端部附近，并且两个端部部分向外弯曲以避免与源极接触层接触。
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公开(公告)号：US06713886B2
公开(公告)日：2004-03-30
申请号：US09827391
申请日：2001-04-06
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： A semiconductor device includes an SRAM section and a logic circuit section formed on a single semiconductor substrate. First and second gate electrode layers located in a first conductive layer, first and second drain-drain contact layers located in a second conductive layer, first and second drain-gate contact layers located in a third conductive layer become conductive layers for forming a flip-flop of the SRAM section. The logic circuit section has no wiring layer at the same level as the first and second drain-drain contact layers.
摘要翻译： 半导体器件包括形成在单个半导体衬底上的SRAM部分和逻辑电路部分。 位于第一导电层中的第一和第二栅极电极层，位于第二导电层中的第一和第二漏极 - 漏极接触层，位于第三导电层中的第一和第二漏极 - 栅极接触层变成导电层， 的SRAM部分。 逻辑电路部分没有与第一和第二漏极 - 漏极接触层处于相同电平的布线层。
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5.发明授权Semiconductor memory device having improved pattern of layers and compact dimensions 失效半导体存储器件具有改进的层的图案和紧凑的尺寸公开(公告)号：US06455899B2
公开(公告)日：2002-09-24
申请号：US09764449
申请日：2001-01-19
IPC分类号： H01L2976
CPC分类号： G11C11/412 , Y10S257/903
摘要： First and second gate electrode layers that are positioned in a first conductive layer, first and second drain-drain contact layers that are positioned in a second conductive layer, and first and second drain-gate contact layers that are positioned in a third conductive layer together form conductive layers for a flip-flop. A sub word line extends in the X-axis direction in the first conductive layer. A VDD wire is disposed extending in the X-axis direction in the second conductive layer. A main word line is disposed extending in the X-axis direction in the third conductive layer. A bit line, a bit line/, a VSS wire, and a VDD wire are disposed extending in the Y-axis direction in the fourth conductive layer.
摘要翻译： 位于第一导电层中的第一和第二栅极电极层，位于第二导电层中的第一和第二漏极 - 漏极接触层以及位于第三导电层中的第一和第二漏极 - 栅极接触层 形成触发器的导电层。 子字线在第一导电层中在X轴方向上延伸。 在第二导电层中，在X轴方向上配置VDD线。 主字线在第三导电层中在X轴方向上延伸设置。 在第四导电层中沿Y轴方向延伸有位线，位线/ VSS线和VDD线。
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6.发明授权Semiconductor memory device having gate electrode, drain-drain contact, and drain-gate contact layers 失效具有栅电极，漏极 - 漏极接触和漏极 - 栅极接触层的半导体存储器件公开(公告)号：US06407463B2
公开(公告)日：2002-06-18
申请号：US09736386
申请日：2000-12-15
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： The drain of a drive transistor Q3 and the drain of a load transistor Q5 are connected by a first drain—drain contact layer. The drain of a drive transistor Q4 and the drain of a load transistor Q6 are connected by a second drain—drain contact layer. The gate electrodes of the drive transistor Q3 and the load transistor Q5 (a first gate electrode layer) are connected to the second drain—drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q4 and the load transistor Q6 (a second gate electrode layer) are connected to the first drain—drain contact layer by a second drain-gate contact layer.
摘要翻译： 驱动晶体管Q3的漏极和负载晶体管Q5的漏极通过第一漏极 - 漏极接触层连接。 驱动晶体管Q4的漏极和负载晶体管Q6的漏极通过第二漏极 - 漏极接触层连接。 驱动晶体管Q3和负载晶体管Q5（第一栅极电极层）的栅电极通过第一漏极 - 栅极接触层连接到第二漏极 - 漏极接触层。 驱动晶体管Q4的栅电极和负载晶体管Q6（第二栅极电极层）通过第二漏极 - 栅极接触层连接到第一漏极 - 漏极接触层。
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公开(公告)号：US06347048B2
公开(公告)日：2002-02-12
申请号：US09841105
申请日：2001-04-25
IPC分类号： G11C1100
CPC分类号： H01L27/1104 , Y10S257/903
摘要： A semiconductor memory device comprising first and second gate electrode layers in a first conductive layer, first and second drain-drain connecting layers in a second conductive layer, and first and second drain-gate connecting layers in a third conductive layer. The first and second drain-gate connecting layers are located higher than the first and second gate electrode layers. Therefore, a source contact layer can be located in the region between gate electrode layers while preventing a contact with the second drain-gate connecting layer.
摘要翻译： 一种半导体存储器件，包括在第一导电层中的第一和第二栅极电极层，第二导电层中的第一和第二漏极 - 漏极连接层，以及第三导电层中的第一和第二漏极 - 栅极连接层。 第一和第二漏极 - 栅极连接层位于比第一和第二栅极电极层高的位置。 因此，源极接触层可以位于栅极电极层之间的区域中，同时防止与第二漏极 - 栅极连接层的接触。
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8.发明授权Semiconductor device with SRAM section including a plurality of memory cells 失效具有包括多个存储单元的SRAM部分的半导体器件公开(公告)号：US06657243B2
公开(公告)日：2003-12-02
申请号：US09945164
申请日：2001-08-31
IPC分类号： G11C1100
CPC分类号： H01L27/1104 , H01L27/0207 , Y10S257/903 , Y10S257/904
摘要： A semiconductor device having an SRAM section in which a p-well, a first n-well, and a second n-well are formed in a semiconductor substrate. Two n-type access transistors and two n-type driver transistors are formed in the p-well. Two p-type load transistors are formed in the first n-well. The second n-well is located under the p-well and the first n-well and also is connected to the first n-well. The potential of the first n-well is supplied from the second n-well. According to the present invention, the SRAM section can be reduced in size.
摘要翻译： 具有在半导体衬底中形成p阱，第一n阱和第二n阱的SRAM部分的半导体器件。 在p阱中形成两个n型存取晶体管和两个n型驱动晶体管。 在第一n阱中形成两个p型负载晶体管。 第二个n阱位于p阱和第一个n阱之下，并且还连接到第一个n阱。 第一个n阱的电位由第二个n阱提供。 根据本发明，可以减小SRAM部分的尺寸。
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公开(公告)号：US06538338B2
公开(公告)日：2003-03-25
申请号：US09876059
申请日：2001-06-08
IPC分类号： H01L2711
CPC分类号： H01L27/1104
摘要： The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain—drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. Driver transistors of one memory cell do not commonly share the n+ type source region with driver transistors of another memory cell.
摘要翻译： 本发明提供了可以减小存储器单元尺寸并校正光接近效应的SRAM。 第一层中的栅极电极层，第二层中的漏极 - 漏极连接层和第三层中的漏极 - 连接层限定了触发器的导电层。 一个存储单元的驱动晶体管与另一个存储单元的驱动晶体管不共用n +型源极区域。
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公开(公告)号：US06469400B2
公开(公告)日：2002-10-22
申请号：US09827155
申请日：2001-04-06
IPC分类号： H01L2711
CPC分类号： H01L27/11 , H01L23/53223 , H01L23/53228 , H01L27/1104 , H01L2924/0002 , H01L2924/00
摘要： First and second gate electrode layers located in a first conductive layer, first and second drain-drain connecting layers located in a second conductive layer, and first and second drain-gate connecting layers located in a third conductive layer become conductive layers for forming a flip-flop. First and second contact-conductive sections are formed in a region from an interlayer dielectric between the first and second conductive layers to an interlayer dielectric between the second and third conductive layers. The first drain-gate connecting layer is connected to the second gate electrode layer with the first contact-conductive section interposed. The second drain-gate connecting layer is connected to the first gate electrode layer with the second contact-conductive section interposed.
摘要翻译： 位于第一导电层中的第一和第二栅极电极层，位于第二导电层中的第一和第二漏极 - 漏极连接层以及位于第三导电层中的第一和第二漏极 - 栅极连接层成为用于形成翻转的导电层 -flop。 第一和第二接触导电部分形成在从第一和第二导电层之间的层间电介质到第二和第三导电层之间的层间电介质的区域中。 第一漏极 - 栅极连接层连接到第二栅电极层，第一接触导电部分插入。 第二漏极 - 栅极连接层连接到第一栅极电极层，插入第二接触导电部分。
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